diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 3 |
2 files changed, 0 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index f3754e00..d140725f 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,6 @@ * while moving to the more standard package naming convention `chisel3` (lowercase c). */ import chisel3._ // required for implicit conversions. -import chisel3.experimental.chiselName import chisel3.util.random.FibonacciLFSR import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage} @@ -617,7 +616,6 @@ package object Chisel { /** Generates a 16-bit linear feedback shift register, returning the register contents. * @param increment optional control to gate when the LFSR updates. */ - @chiselName def apply(increment: Bool = true.B): UInt = VecInit( FibonacciLFSR diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index b21bd04f..f8c8f9e9 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -7,7 +7,6 @@ package chisel3.util import chisel3._ import chisel3.experimental.{requireIsChiselType, DataMirror, Direction} -import chisel3.internal.naming._ // can't use chisel3_ version because of compile order import scala.annotation.nowarn @@ -136,7 +135,6 @@ object Decoupled { * * @note unsafe (and will error) on the producer (input) side of an IrrevocableIO */ - @chiselName def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { require( DataMirror.directionOf(irr.bits) == Direction.Output, @@ -403,7 +401,6 @@ object Queue { * consumer.io.in <> Queue(producer.io.out, 16) * }}} */ - @chiselName def irrevocable[T <: Data]( enq: ReadyValidIO[T], entries: Int = 2, |