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-rw-r--r--src/main/scala/chisel3/stage/ChiselAnnotations.scala6
-rw-r--r--src/main/scala/chisel3/stage/ChiselStage.scala22
-rw-r--r--src/main/scala/chisel3/stage/phases/Elaborate.scala15
3 files changed, 17 insertions, 26 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index bbe86ab4..04246fc5 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -56,13 +56,9 @@ case class ChiselGeneratorAnnotation(gen: () => RawModule) extends NoTargetAnnot
/** Run elaboration on the Chisel module generator function stored by this [[firrtl.annotations.Annotation]]
*/
- def elaborate: AnnotationSeq = try {
+ def elaborate: AnnotationSeq = {
val (circuit, dut) = Builder.build(Module(gen()))
Seq(ChiselCircuitAnnotation(circuit), DesignAnnotation(dut))
- } catch {
- case e @ (_: OptionsException | _: ChiselException) => throw e
- case e: Throwable =>
- throw new ChiselException(s"Exception thrown when elaborating ChiselGeneratorAnnotation", e)
}
}
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index aae7ad8d..1bcf5124 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -13,7 +13,7 @@ import firrtl.{
VerilogEmitter,
SystemVerilogEmitter
}
-import firrtl.options.{Dependency, Phase, PhaseManager, Shell, Stage, StageError, StageMain}
+import firrtl.options.{Dependency, Phase, PhaseManager, Shell, Stage, StageMain}
import firrtl.options.phases.DeletedWrapper
import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlCli, RunFirrtlTransformAnnotation}
import firrtl.options.Viewer.view
@@ -28,7 +28,7 @@ class ChiselStage extends Stage {
override def prerequisites = Seq.empty
override def optionalPrerequisites = Seq.empty
- override def optionalPrerequisiteOf = Seq.empty
+ override def optionalPrerequisiteOf = Seq(Dependency[firrtl.stage.FirrtlStage])
override def invalidates(a: Phase) = false
val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli
@@ -42,23 +42,7 @@ class ChiselStage extends Stage {
}
}
- def run(annotations: AnnotationSeq): AnnotationSeq = try {
- phaseManager.transform(annotations)
- } catch {
- case ce: ChiselException =>
- val stackTrace = if (!view[ChiselOptions](annotations).printFullStackTrace) {
- ce.chiselStackTrace
- } else {
- val sw = new StringWriter
- ce.printStackTrace(new PrintWriter(sw))
- sw.toString
- }
- Predef
- .augmentString(stackTrace)
- .lines
- .foreach(line => println(s"${ErrorLog.errTag} $line"))
- throw new StageError(cause=ce)
- }
+ def run(annotations: AnnotationSeq): AnnotationSeq = phaseManager.transform(annotations)
/** Convert a Chisel module to a CHIRRTL string
* @param gen a call-by-name Chisel module
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala
index 04cfc33e..df39b66b 100644
--- a/src/main/scala/chisel3/stage/phases/Elaborate.scala
+++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala
@@ -6,6 +6,7 @@ import java.io.{PrintWriter, StringWriter}
import chisel3.ChiselException
import chisel3.internal.ErrorLog
+import chisel3.internal.ExceptionHelpers.ThrowableHelpers
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOptions}
import firrtl.AnnotationSeq
import firrtl.options.Viewer.view
@@ -21,8 +22,18 @@ class Elaborate extends Phase {
override def invalidates(a: Phase) = false
def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {
- case a: ChiselGeneratorAnnotation => a.elaborate
- case a => Some(a)
+ case a: ChiselGeneratorAnnotation => try {
+ a.elaborate
+ } catch {
+ /* if any throwable comes back and we're in "stack trace trimming" mode, then print an error and trim the stack trace
+ */
+ case scala.util.control.NonFatal(a) =>
+ if (!view[ChiselOptions](annotations).printFullStackTrace) {
+ a.trimStackTraceToUserCode()
+ }
+ throw(a)
+ }
+ case a => Some(a)
}
}