diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/Chisel/Reg.scala | 10 | ||||
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/Emitter.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 3 |
3 files changed, 10 insertions, 6 deletions
diff --git a/src/main/scala/Chisel/Reg.scala b/src/main/scala/Chisel/Reg.scala index f166c84b..e69061c5 100644 --- a/src/main/scala/Chisel/Reg.scala +++ b/src/main/scala/Chisel/Reg.scala @@ -45,10 +45,12 @@ object Reg { // to resolve all use cases. If the type inferencer / implicit resolution // system improves, this may be changed. val x = makeType(t, next, init) - val (resetEn, resetVal) = - if (init != null) (Node(x._parent.get.reset), init) - else (ULit(0, Width(1)), x) - pushCommand(DefRegister(x, Node(x._parent.get.clock), resetEn, resetVal.ref)) // TODO multi-clock + val clock = Node(x._parent.get.clock) // TODO multi-clock + if (init == null) { + pushCommand(DefReg(x, clock)) + } else { + pushCommand(DefRegInit(x, clock, Node(x._parent.get.reset), init.ref)) + } if (next != null) { x := next } diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala index 8597454a..2765efa8 100644 --- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala +++ b/src/main/scala/Chisel/internal/firrtl/Emitter.scala @@ -12,7 +12,8 @@ private class Emitter(circuit: Circuit) { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})" case e: DefWire => s"wire ${e.name} : ${e.id.toType}" case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}" - case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}" + case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}" + case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]" case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index 5612f1af..ec9b9e36 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -149,7 +149,8 @@ abstract class Definition extends Command { } case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition case class DefWire(id: Data) extends Definition -case class DefRegister(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +case class DefReg(id: Data, clock: Arg) extends Definition +case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int) extends Definition case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition |