diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index f95bb17c..6fb67585 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -38,8 +38,8 @@ object Pipe def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = { if (latency == 0) { val out = Wire(Valid(enqBits)) - out.valid <> enqValid - out.bits <> enqBits + out.valid := enqValid + out.bits := enqBits out } else { val v = RegNext(enqValid, false.B) |