diff options
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/util/MixedVec.scala | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala index e09cdc4a..eeac76ea 100644 --- a/src/main/scala/chisel3/util/MixedVec.scala +++ b/src/main/scala/chisel3/util/MixedVec.scala @@ -77,18 +77,21 @@ final class MixedVec[T <: Data](private val eltsIn: Seq[T]) extends Record with /** * Dynamically (via a mux) retrieve the element at the given index. + * This is implemented via a mux with the width of the widest element in this MixedVec. + * For example, a MixedVec of type Seq(UInt(4.W), UInt(8.W)) will create an 8-bit mux for this operation. + * Note: it is up to the user to process the resultant UInt (e.g. unflatten, etc). * - * @param index Index with which to retrieve. - * @return Retrieved index. + * @param index Index to retrieve. If the index is out of range, it will return the first element. + * @return Retrieved index as a UInt with the width of the widest element. */ - def apply(index: UInt): T = { + def apply(index: UInt): UInt = { requireIsHardware(index, "index must be hardware") if (length < 1) { throw new IndexOutOfBoundsException("Collection is empty") } - MuxLookup(index, elts.head, elts.zipWithIndex.map { case (el, el_index) => el_index.U -> el }) + MuxLookup(index, elts.head.asUInt, elts.zipWithIndex.map { case (el, el_index) => el_index.U -> el.asUInt }) } /** Strong bulk connect, assigning elements in this MixedVec from elements in a Seq. |