diff options
Diffstat (limited to 'src/main/scala/chisel3')
3 files changed, 77 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala b/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala new file mode 100644 index 00000000..6b4bb8f0 --- /dev/null +++ b/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.util + +import chisel3._ + +/** Map each bit to the logical OR of itself and all bits with lower index + * + * Here `scanLeft` means "start from the left and iterate to the right, where left is the lowest index", a common operation on arrays and lists. + * @example {{{ + * scanLeftOr("b00001000".U(8.W)) // Returns "b11111000".U + * scanLeftOr("b00010100".U(8.W)) // Returns "b11111100".U + * scanLeftOr("b00000000".U(8.W)) // Returns "b00000000".U + * }}} + */ +object scanLeftOr { + def apply(data: UInt): UInt = { + val width = data.widthOption match { + case Some(w) => w + case None => throw new IllegalArgumentException("Cannot call scanLeftOr on data with unknown width.") + } + + def helper(s: Int, x: UInt): UInt = + if (s >= width) x else helper(s + s, x | (x << s)(width - 1, 0)) + helper(1, data)(width - 1, 0) + } +} + +/** Map each bit to the logical OR of itself and all bits with higher index + * + * Here `scanRight` means "start from the right and iterate to the left, where right is the highest index", a common operation on arrays and lists. + * @example {{{ + * scanRightOr("b00001000".U) // Returns "b00001111".U + * scanRightOr("b00010100".U) // Returns "b00011111".U + * scanRightOr("b00000000".U) // Returns "b00000000".U + * }}} + */ +object scanRightOr { + def apply(data: UInt): UInt = { + val width = data.widthOption match { + case Some(w) => w + case None => throw new IllegalArgumentException("Cannot call scanRightOr on data with unknown width.") + } + def helper(s: Int, x: UInt): UInt = + if (s >= width) x else helper(s + s, x | (x >> s)) + helper(1, data)(width - 1, 0) + } +} diff --git a/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala b/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala index e742fd66..00fa0f9c 100644 --- a/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala +++ b/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala @@ -31,10 +31,15 @@ object TruthTable { /** Convert a table and default output into a [[TruthTable]]. */ def apply(table: Iterable[(BitPat, BitPat)], default: BitPat, sort: Boolean = true): TruthTable = { - require(table.map(_._1.getWidth).toSet.size == 1, "input width not equal.") + val inputWidth = table.map(_._1.getWidth).max require(table.map(_._2.getWidth).toSet.size == 1, "output width not equal.") val outputWidth = table.map(_._2.getWidth).head - val mergedTable = table + val mergedTable = table.map { + // pad input signals if necessary + case (in, out) if inputWidth > in.width => + (BitPat.N(inputWidth - in.width) ## in, out) + case (in, out) => (in, out) + } .groupBy(_._1.toString) .map { case (key, values) => diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala index b926a15c..c301ff98 100644 --- a/src/main/scala/chisel3/verilog.scala +++ b/src/main/scala/chisel3/verilog.scala @@ -4,7 +4,29 @@ import chisel3.stage.ChiselStage import firrtl.AnnotationSeq object getVerilogString { + + /** + * Returns a string containing the Verilog for the module specified by + * the target. + * + * @param gen the module to be converted to Verilog + * @return a string containing the Verilog for the module specified by + * the target + */ def apply(gen: => RawModule): String = ChiselStage.emitVerilog(gen) + + /** + * Returns a string containing the Verilog for the module specified by + * the target accepting arguments and annotations + * + * @param gen the module to be converted to Verilog + * @param args arguments to be passed to the compiler + * @param annotations annotations to be passed to the compiler + * @return a string containing the Verilog for the module specified by + * the target + */ + def apply(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String = + (new ChiselStage).emitVerilog(gen, args, annotations) } object emitVerilog { |