4 files changed, 0 insertions, 10 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 220a12b1..06821a25 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -6,7 +6,6 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs
   * (selects) at most one.
@@ -115,7 +114,6 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T
   * consumer.io.in <> arb.io.out
   * }}}
   */
-@chiselName
 class RRArbiter[T <: Data](val gen: T, val n: Int) extends LockingRRArbiter[T](gen, n, 1)
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -131,7 +129,6 @@ class RRArbiter[T <: Data](val gen: T, val n: Int) extends LockingRRArbiter[T](g
   * consumer.io.in <> arb.io.out
   * }}}
   */
-@chiselName
 class Arbiter[T <: Data](val gen: T, val n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index df60f059..9e4890a9 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -6,7 +6,6 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** Returns the base-2 integer logarithm of an UInt.
   *
@@ -22,7 +21,6 @@ object Log2 {
 
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     */
-  @chiselName
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
       0.U
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 0d1b8db1..be6e3257 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -4,7 +4,6 @@ package chisel3.util
 
 import chisel3._
 import chisel3.experimental.AffectsChiselPrefix
-import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** Used to generate an inline (logic directly in the containing Module, no internal Module is created)
   * hardware counter.
@@ -113,7 +112,6 @@ object Counter {
     * @return tuple of the counter value and whether the counter will wrap (the value is at
     * maximum and the condition is true).
     */
-  @chiselName
   def apply(cond: Bool, n: Int): (UInt, Bool) = {
     val c = new Counter(n)
     val wrap = WireInit(false.B)
@@ -129,7 +127,6 @@ object Counter {
     * @return tuple of the counter value and whether the counter will wrap (the value is at
     * maximum and the condition is true).
     */
-  @chiselName
   def apply(r: Range, enable: Bool = true.B, reset: Bool = false.B): (UInt, Bool) = {
     val c = new Counter(r)
     val wrap = WireInit(false.B)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 42717b66..f02a4116 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -233,7 +233,6 @@ class QueueIO[T <: Data](
   * consumer.io.in <> q.io.deq
   * }}}
   */
-@chiselName
 class Queue[T <: Data](
   val gen:            T,
   val entries:        Int,
@@ -345,7 +344,6 @@ object Queue {
     * }}}
     */
   @nowarn("cat=deprecation&msg=TransitName")
-  @chiselName
   def apply[T <: Data](
     enq:            ReadyValidIO[T],
     entries:        Int = 2,