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-rw-r--r--src/main/scala/chisel3/util/Reg.scala8
1 files changed, 3 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 713a3b2e..00005e3a 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -53,12 +53,10 @@ object ShiftRegister
* @param n number of cycles to delay
* @param en enable the shift
*/
- def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
+ def apply[T <: Data](in: T, n: Int, en: Bool = true.B): T = {
// The order of tests reflects the expected use cases.
- if (n == 1) {
- RegEnable(in, en)
- } else if (n != 0) {
- RegNext(apply(in, n-1, en))
+ if (n != 0) {
+ RegEnable(apply(in, n-1, en), en)
} else {
in
}