1 files changed, 31 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index ddb74dd6..89381c11 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -12,7 +12,10 @@ object RegEnable {
     * val regWithEnable = RegEnable(nextVal, ena)
     * }}}
     */
-  def apply[T <: Data](next: T, enable: Bool): T = {
+  def apply[T <: Data](
+    @deprecatedName('next, "Chisel 3.5") next:     T,
+    @deprecatedName('enable, "Chisel 3.5") enable: Bool
+  ): T = {
     val r = Reg(chiselTypeOf(next))
     when(enable) { r := next }
     r
@@ -24,7 +27,11 @@ object RegEnable {
     * val regWithEnableAndReset = RegEnable(nextVal, 0.U, ena)
     * }}}
     */
-  def apply[T <: Data](next: T, init: T, enable: Bool): T = {
+  def apply[T <: Data](
+    @deprecatedName('next, "Chisel 3.5") next:     T,
+    @deprecatedName('init, "Chisel 3.5") init:     T,
+    @deprecatedName('enable, "Chisel 3.5") enable: Bool
+  ): T = {
     val r = RegInit(init)
     when(enable) { r := next }
     r
@@ -43,7 +50,11 @@ object ShiftRegister {
     * val regDelayTwo = ShiftRegister(nextVal, 2, ena)
     * }}}
     */
-  def apply[T <: Data](in: T, n: Int, en: Bool = true.B): T = ShiftRegisters(in, n, en).lastOption.getOrElse(in)
+  def apply[T <: Data](
+    @deprecatedName('in, "Chisel 3.5") in: T,
+    @deprecatedName('n, "Chisel 3.5") n:   Int,
+    @deprecatedName('en, "Chisel 3.5") en: Bool = true.B
+  ): T = ShiftRegisters(in, n, en).lastOption.getOrElse(in)
 
   /** Returns the n-cycle delayed version of the input signal with reset initialization.
     *
@@ -56,7 +67,12 @@ object ShiftRegister {
     * val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena)
     * }}}
     */
-  def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T =
+  def apply[T <: Data](
+    @deprecatedName('in, "Chisel 3.5") in:               T,
+    @deprecatedName('n, "Chisel 3.5") n:                 Int,
+    @deprecatedName('resetData, "Chisel 3.5") resetData: T,
+    @deprecatedName('en, "Chisel 3.5") en:               Bool
+  ): T =
     ShiftRegisters(in, n, resetData, en).lastOption.getOrElse(in)
 }
 
@@ -68,7 +84,11 @@ object ShiftRegisters {
     * @param n  number of cycles to delay
     * @param en enable the shift
     */
-  def apply[T <: Data](in: T, n: Int, en: Bool = true.B): Seq[T] =
+  def apply[T <: Data](
+    @deprecatedName('in, "Chisel 3.5") in: T,
+    @deprecatedName('n, "Chisel 3.5") n:   Int,
+    @deprecatedName('en, "Chisel 3.5") en: Bool = true.B
+  ): Seq[T] =
     Seq.iterate(in, n + 1)(util.RegEnable(_, en)).drop(1)
 
   /** Returns delayed input signal registers with reset initialization from 1 to n.
@@ -78,6 +98,11 @@ object ShiftRegisters {
     * @param resetData reset value for each register in the shift
     * @param en        enable the shift
     */
-  def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): Seq[T] =
+  def apply[T <: Data](
+    @deprecatedName('in, "Chisel 3.5") in:               T,
+    @deprecatedName('n, "Chisel 3.5") n:                 Int,
+    @deprecatedName('resetData, "Chisel 3.5") resetData: T,
+    @deprecatedName('en, "Chisel 3.5") en:               Bool
+  ): Seq[T] =
     Seq.iterate(in, n + 1)(util.RegEnable(_, resetData, en)).drop(1)
 }