1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index d35046af..bcd65a1b 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -19,9 +19,16 @@ import chisel3.internal.naming._  // can't use chisel3_ version because of compi
   */
 abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
 {
+  // Compatibility hack for rocket-chip
+  private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
+    case (true, Some(module: chisel3.core.ImplicitModule))
+        if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
+    case _ => gen
+  }
+
   val ready = Input(Bool())
   val valid = Output(Bool())
-  val bits  = Output(gen.chiselCloneType)
+  val bits  = Output(genType)
 }
 
 object ReadyValidIO {
@@ -200,7 +207,7 @@ class Queue[T <: Data](gen: T,
     gen
   } else {
     if (DataMirror.internal.isSynthesizable(gen)) {
-      gen.chiselCloneType
+      chiselTypeOf(gen)
     } else {
       gen
     }
@@ -226,7 +233,7 @@ class Queue[T <: Data](gen: T,
   when (do_deq) {
     deq_ptr.inc()
   }
-  when (do_enq != do_deq) {
+  when (do_enq =/= do_deq) {
     maybe_full := do_enq
   }