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-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala17
1 files changed, 11 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index a422b5fe..b5f491ef 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -7,10 +7,19 @@ package chisel3.util
import chisel3._
+/** Returns the base-2 integer logarithm of an UInt.
+ *
+ * @note The result is truncated, so e.g. Log2(13.U) === 3.U
+ *
+ * @example {{{
+ * Log2(8.U) // evaluates to 3.U
+ * Log2(13.U) // evaluates to 3.U (truncation)
+ * Log2(myUIntWire)
+ * }}}
+ *
+ */
object Log2 {
/** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
- *
- * @note The result is truncated, so e.g. Log2(13.U) === 3.U
*/
def apply(x: Bits, width: Int): UInt = {
if (width < 2) {
@@ -28,10 +37,6 @@ object Log2 {
}
}
- /** Returns the base-2 integer logarithm of an UInt.
- *
- * @note The result is truncated, so e.g. Log2(13.U) === 3.U
- */
def apply(x: Bits): UInt = apply(x, x.getWidth)
private def divideAndConquerThreshold = 4