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-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala2
-rw-r--r--src/main/scala/chisel3/testers/TesterDriver.scala74
-rw-r--r--src/main/scala/chisel3/testers/package.scala5
3 files changed, 44 insertions, 37 deletions
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 99002660..5e28a523 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -13,7 +13,7 @@ class BasicTester extends Module() {
// The testbench has no IOs, rather it should communicate using printf, assert, and stop.
val io = IO(new Bundle() {})
- def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
+ def popCount(n: Long): Int = n.toBinaryString.count(_ == '1')
/** Ends the test reporting success.
*
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index e87aceca..9c4b2da9 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -16,24 +16,27 @@ import firrtl.transforms.BlackBoxSourceHelper.writeResourceToDirectory
object TesterDriver extends BackendCompilationUtilities {
private[chisel3] trait Backend extends NoTargetAnnotation with Unserializable {
- def execute(t: () => BasicTester,
- additionalVResources: Seq[String] = Seq(),
- annotations: AnnotationSeq = Seq(),
- nameHint: Option[String] = None
- ): Boolean
+ def execute(
+ t: () => BasicTester,
+ additionalVResources: Seq[String] = Seq(),
+ annotations: AnnotationSeq = Seq(),
+ nameHint: Option[String] = None
+ ): Boolean
}
case object VerilatorBackend extends Backend {
+
/** For use with modules that should successfully be elaborated by the
- * frontend, and which can be turned into executables with assertions. */
- def execute(t: () => BasicTester,
- additionalVResources: Seq[String] = Seq(),
- annotations: AnnotationSeq = Seq(),
- nameHint: Option[String] = None
- ): Boolean = {
+ * frontend, and which can be turned into executables with assertions.
+ */
+ def execute(
+ t: () => BasicTester,
+ additionalVResources: Seq[String] = Seq(),
+ annotations: AnnotationSeq = Seq(),
+ nameHint: Option[String] = None
+ ): Boolean = {
val pm = new PhaseManager(
- targets = Seq(Dependency[AddImplicitTesterDirectory],
- Dependency[Emitter],
- Dependency[Convert]))
+ targets = Seq(Dependency[AddImplicitTesterDirectory], Dependency[Emitter], Dependency[Convert])
+ )
val annotationsx = pm.transform(ChiselGeneratorAnnotation(finishWrapper(t)) +: annotations)
@@ -41,7 +44,7 @@ object TesterDriver extends BackendCompilationUtilities {
val path = annotationsx.collectFirst { case TargetDirAnnotation(dir) => dir }.map(new File(_)).get
// Copy CPP harness and other Verilog sources from resources into files
- val cppHarness = new File(path, "top.cpp")
+ val cppHarness = new File(path, "top.cpp")
copyResourceToFile("/chisel3/top.cpp", cppHarness)
// NOTE: firrtl.Driver.execute() may end up copying these same resources in its BlackBoxSourceHelper code.
// As long as the same names are used for the output files, and we avoid including duplicate files
@@ -54,8 +57,10 @@ object TesterDriver extends BackendCompilationUtilities {
(new FirrtlStage).execute(Array("--compiler", "verilog"), annotationsx)
// Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
- if ((verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
- cppToExe(target, path)).! == 0) {
+ if (
+ (verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+ cppToExe(target, path)).! == 0
+ ) {
executeExpectingSuccess(target, path)
} else {
false
@@ -77,21 +82,26 @@ object TesterDriver extends BackendCompilationUtilities {
override def invalidates(a: Phase) = false
override def transform(a: AnnotationSeq) = a.flatMap {
- case a@ ChiselCircuitAnnotation(circuit) =>
- Seq(a, TargetDirAnnotation(
- firrtl.util.BackendCompilationUtilities.createTestDirectory(circuit.name)
- .getAbsolutePath
- .toString))
+ case a @ ChiselCircuitAnnotation(circuit) =>
+ Seq(
+ a,
+ TargetDirAnnotation(
+ firrtl.util.BackendCompilationUtilities.createTestDirectory(circuit.name).getAbsolutePath.toString
+ )
+ )
case a => Seq(a)
}
}
/** For use with modules that should successfully be elaborated by the
- * frontend, and which can be turned into executables with assertions. */
- def execute(t: () => BasicTester,
- additionalVResources: Seq[String] = Seq(),
- annotations: AnnotationSeq = Seq(),
- nameHint: Option[String] = None): Boolean = {
+ * frontend, and which can be turned into executables with assertions.
+ */
+ def execute(
+ t: () => BasicTester,
+ additionalVResources: Seq[String] = Seq(),
+ annotations: AnnotationSeq = Seq(),
+ nameHint: Option[String] = None
+ ): Boolean = {
val backendAnnotations = annotations.collect { case anno: Backend => anno }
val backendAnnotation = if (backendAnnotations.length == 1) {
@@ -109,11 +119,11 @@ object TesterDriver extends BackendCompilationUtilities {
* The finish method is a hook for code that augments the circuit built in the constructor.
*/
def finishWrapper(test: () => BasicTester): () => BasicTester = { () =>
- {
- val tester = test()
- tester.finish()
- tester
- }
+ {
+ val tester = test()
+ tester.finish()
+ tester
+ }
}
}
diff --git a/src/main/scala/chisel3/testers/package.scala b/src/main/scala/chisel3/testers/package.scala
index f60f7cc2..f20a7977 100644
--- a/src/main/scala/chisel3/testers/package.scala
+++ b/src/main/scala/chisel3/testers/package.scala
@@ -3,8 +3,5 @@
package chisel3
/** The testers package provides the basic interface for chisel testers.
- *
*/
-package object testers {
-
-}
+package object testers {}