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-rw-r--r--src/main/scala/chisel3/Driver.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a0713379..ab51ad25 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,7 +95,7 @@ trait BackendCompilationUtilities {
/** Generates a Verilator invocation to convert Verilog sources to C++
* simulation sources.
*
- * The Verilator prefix will be V$dutFile, and running this will generate
+ * The Verilator prefix will be V\$dutFile, and running this will generate
* C++ sources and headers as well as a makefile to compile them.
*
* @param dutFile name of the DUT .v without the .v extension
@@ -119,13 +119,13 @@ trait BackendCompilationUtilities {
"-Wno-WIDTH",
"-Wno-STMTDLY",
"--trace",
- "-O0",
+ "-O1",
"--top-module", topModule,
"+define+TOP_TYPE=V" + dutFile,
s"+define+PRINTF_COND=!$topModule.reset",
s"+define+STOP_COND=!$topModule.reset",
"-CFLAGS",
- s"""-Wno-undefined-bool-conversion -O0 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
+ s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
"-Mdir", dir.toString,
"--exe", cppHarness.toString)
System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex