1 files changed, 38 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 25d25425..642f7caa 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -2,7 +2,7 @@
 
 package chisel3
 
-import chisel3.internal.firrtl.Emitter
+import chisel3.internal.firrtl.Converter
 import chisel3.experimental.{RawModule, RunFirrtlTransform}
 
 import java.io._
@@ -92,7 +92,9 @@ object Driver extends BackendCompilationUtilities {
     */
   def elaborate[T <: RawModule](gen: () => T): Circuit = internal.Builder.build(Module(gen()))
 
-  def emit[T <: RawModule](gen: () => T): String = Emitter.emit(elaborate(gen))
+  def toFirrtl(ir: Circuit): firrtl.ir.Circuit = Converter.convert(ir)
+
+  def emit[T <: RawModule](gen: () => T): String = Driver.emit(elaborate(gen))
 
   def emit[T <: RawModule](ir: Circuit): String = Emitter.emit(ir)
 
@@ -108,14 +110,41 @@ object Driver extends BackendCompilationUtilities {
     }
   }
 
+  /** Dumps the elaborated Circuit to FIRRTL
+    *
+    * If no File is given as input, it will dump to a default filename based on the name of the
+    * Top Module
+    *
+    * @param c Elaborated Chisel Circuit
+    * @param optName Optional File to dump to
+    * @return The File the circuit was dumped to
+    */
   def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
     val f = optName.getOrElse(new File(ir.name + ".fir"))
     val w = new FileWriter(f)
-    w.write(Emitter.emit(ir))
+    w.write(Driver.emit(ir))
     w.close()
     f
   }
 
+  /** Dumps the elaborated Circuit to ProtoBuf
+    *
+    * If no File is given as input, it will dump to a default filename based on the name of the
+    * Top Module
+    *
+    * @param c Elaborated Chisel Circuit
+    * @param optFile Optional File to dump to
+    * @return The File the circuit was dumped to
+    */
+  def dumpProto(c: Circuit, optFile: Option[File]): File = {
+    val f = optFile.getOrElse(new File(c.name + ".pb"))
+    val ostream = new java.io.FileOutputStream(f)
+    // Lazily convert modules to make intermediate objects garbage collectable
+    val modules = c.components.map(m => () => Converter.convert(m))
+    firrtl.proto.ToProto.writeToStreamFast(ostream, ir.NoInfo, modules, c.name)
+    f
+  }
+
   private var target_dir: Option[String] = None
   def parseArgs(args: Array[String]): Unit = {
     for (i <- 0 until args.size) {
@@ -145,8 +174,10 @@ object Driver extends BackendCompilationUtilities {
     val firrtlOptions = optionsManager.firrtlOptions
     val chiselOptions = optionsManager.chiselOptions
 
-    // use input because firrtl will be reading this
-    val firrtlString = Emitter.emit(circuit)
+    val firrtlCircuit = Converter.convert(circuit)
+
+    // Still emit to leave an artifact (and because this always has been the behavior)
+    val firrtlString = Driver.emit(circuit)
     val firrtlFileName = firrtlOptions.getInputFileName(optionsManager)
     val firrtlFile = new File(firrtlFileName)
 
@@ -154,6 +185,7 @@ object Driver extends BackendCompilationUtilities {
     w.write(firrtlString)
     w.close()
 
+    // Emit the annotations because it has always been the behavior
     val annotationFile = new File(optionsManager.getBuildFileName("anno.json"))
     val af = new FileWriter(annotationFile)
     val firrtlAnnos = circuit.annotations.map(_.toFirrtl)
@@ -174,7 +206,7 @@ object Driver extends BackendCompilationUtilities {
                        }
     /* This passes the firrtl source and annotations directly to firrtl */
     optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(
-      firrtlSource = Some(firrtlString),
+      firrtlCircuit = Some(firrtlCircuit),
       annotations = optionsManager.firrtlOptions.annotations ++ firrtlAnnos,
       customTransforms = optionsManager.firrtlOptions.customTransforms ++ transforms.toList)