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Diffstat (limited to 'src/main/scala/Chisel/utils.scala')
| -rw-r--r-- | src/main/scala/Chisel/utils.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala index f1c5e484..90c59e9d 100644 --- a/src/main/scala/Chisel/utils.scala +++ b/src/main/scala/Chisel/utils.scala @@ -431,12 +431,14 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo val lockIdx = if(count > 1) Reg(init=UInt(n-1)) else UInt(n-1) val chosen = Wire(UInt(width = log2Up(n))) - for ((g, i) <- grant.zipWithIndex) - io.in(i).ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits io.chosen := chosen + io.in(chosen).ready := Bool(false) // XXX FIRRTL workaround + for ((g, i) <- grant.zipWithIndex) + io.in(i).ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + if(count > 1){ val cnt = Reg(init=UInt(0, width = log2Up(count))) val cnt_next = cnt + UInt(1) |