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Diffstat (limited to 'src/main/scala/Chisel/utils.scala')
| -rw-r--r-- | src/main/scala/Chisel/utils.scala | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala index fe8329a7..5756fee0 100644 --- a/src/main/scala/Chisel/utils.scala +++ b/src/main/scala/Chisel/utils.scala @@ -94,9 +94,7 @@ object Mux1H if (in.tail.isEmpty) in.head._2 else { val masked = in map {case (s, i) => Mux(s, i.toBits, Bits(0))} - val width = - if (in.forall(_._2.knownWidth)) Some(in.map(_._2.getWidth).max) - else None + val width = in.map(_._2.width).reduce(_ max _) in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } } |