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Diffstat (limited to 'src/main/scala/Chisel/CoreUtil.scala')
| -rw-r--r-- | src/main/scala/Chisel/CoreUtil.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala index 9027711b..eed90410 100644 --- a/src/main/scala/Chisel/CoreUtil.scala +++ b/src/main/scala/Chisel/CoreUtil.scala @@ -4,7 +4,7 @@ package Chisel import internal._ import internal.Builder.pushCommand -import firrtl._ +import internal.firrtl._ object assert { /** Checks for a condition to be valid in the circuit at all times. If the |