diff options
Diffstat (limited to 'integration-tests/src/test')
4 files changed, 126 insertions, 109 deletions
diff --git a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala index 35d1a299..20f3443a 100644 --- a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala +++ b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala @@ -10,12 +10,12 @@ import firrtl.annotations.MemoryArrayInitAnnotation import org.scalatest.flatspec.AnyFlatSpec class MemFormalSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { - behavior of "SyncReadMem read enable" + behavior.of("SyncReadMem read enable") private def check(mod: Boolean => ReadEnTestModule, alwaysEnabeld: Boolean = false): Unit = { // we first check that the read is enabled when it should be verify(mod(true), Seq(BoundedCheck(4))) - if(!alwaysEnabeld) { + if (!alwaysEnabeld) { // now we check that it is disabled, when it should be // however, note that this check is not exhaustive/complete! assertThrows[FailedBoundedCheckException] { @@ -65,9 +65,9 @@ abstract class ReadEnTestModule(testShouldRead: Boolean) extends Module { }) // the first cycle after reset, the data will be arbitrary - val firstCycle = RegNext(false.B, init=true.B) + val firstCycle = RegNext(false.B, init = true.B) - if(testShouldRead) { + if (testShouldRead) { when(!firstCycle && RegNext(shouldRead)) { verification.assert(out === RegNext(addr)) } diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala index 2d50555e..c75113f6 100644 --- a/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala +++ b/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala @@ -9,11 +9,10 @@ import org.scalatest.flatspec.AnyFlatSpec import chiseltest._ import chiseltest.formal._ -class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { - val xor = TruthTable.fromString( - """10->1 - |01->1 - | 0""".stripMargin) +class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { + val xor = TruthTable.fromString("""10->1 + |01->1 + | 0""".stripMargin) def minimizer: Minimizer = QMCMinimizer @@ -23,7 +22,8 @@ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { "decoder" should "fail with a incorrect DecodeTableAnnotation" in { val annos = Seq( - DecodeTableAnnotation(ReferenceTarget("", "", Nil, "", Nil), + DecodeTableAnnotation( + ReferenceTarget("", "", Nil, "", Nil), """10->1 |01->1 | 0""".stripMargin, @@ -38,14 +38,16 @@ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { "decoder" should "success with a correct DecodeTableAnnotation" in { val annos = Seq( - DecodeTableAnnotation(ReferenceTarget("", "", Nil, "", Nil), + DecodeTableAnnotation( + ReferenceTarget("", "", Nil, "", Nil), """10->1 |01->1 | 0""".stripMargin, - QMCMinimizer.minimize(TruthTable.fromString( - """10->1 - |01->1 - | 0""".stripMargin)).toString + QMCMinimizer + .minimize(TruthTable.fromString("""10->1 + |01->1 + | 0""".stripMargin)) + .toString ) ) verify(new DecodeTestModule(minimizer, table = xor), BoundedCheck(1) +: annos) diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala index 6c8eb4b4..d0f16701 100644 --- a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala +++ b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala @@ -11,7 +11,7 @@ class ScanLeftOrTestModule(width: Int) extends Module { val input = IO(Input(UInt(width.W))) var lsb = false.B - val vec = for(b <- input.asBools) yield { + val vec = for (b <- input.asBools) yield { val cur = b || lsb lsb = cur cur @@ -34,13 +34,13 @@ class ScanRightOrTestModule(width: Int) extends Module { class scanOrTest extends AnyFlatSpec with ChiselScalatestTester with Formal { "scanLeftOr" should "compute correctly" in { - for(i <- 1 to 16) { + for (i <- 1 to 16) { verify(new ScanLeftOrTestModule(i), Seq(BoundedCheck(1))) } } "scanRightOr" should "compute correctly" in { - for(i <- 1 to 16) { + for (i <- 1 to 16) { verify(new ScanRightOrTestModule(i), Seq(BoundedCheck(1))) } } diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala index 2d3e073c..0b6d8e91 100644 --- a/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala +++ b/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala @@ -34,82 +34,92 @@ trait MinimizerSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { // making optimization opportunities to decoder algorithms "case0" should "pass" in { - minimizerTest(TruthTable( - Map( - // BitPat("b000") -> BitPat("b0"), - BitPat("b001") -> BitPat("b?"), - BitPat("b010") -> BitPat("b?"), - // BitPat("b011") -> BitPat("b0"), - BitPat("b100") -> BitPat("b1"), - BitPat("b101") -> BitPat("b1"), - // BitPat("b110") -> BitPat("b0"), - BitPat("b111") -> BitPat("b1") - ), - BitPat("b0") - )) + minimizerTest( + TruthTable( + Map( + // BitPat("b000") -> BitPat("b0"), + BitPat("b001") -> BitPat("b?"), + BitPat("b010") -> BitPat("b?"), + // BitPat("b011") -> BitPat("b0"), + BitPat("b100") -> BitPat("b1"), + BitPat("b101") -> BitPat("b1"), + // BitPat("b110") -> BitPat("b0"), + BitPat("b111") -> BitPat("b1") + ), + BitPat("b0") + ) + ) } "case1" should "pass" in { - minimizerTest(TruthTable( - Map( - BitPat("b000") -> BitPat("b0"), - BitPat("b001") -> BitPat("b?"), - BitPat("b010") -> BitPat("b?"), - BitPat("b011") -> BitPat("b0"), - // BitPat("b100") -> BitPat("b1"), - // BitPat("b101") -> BitPat("b1"), - BitPat("b110") -> BitPat("b0"), - // BitPat("b111") -> BitPat("b1") - ), - BitPat("b1") - )) + minimizerTest( + TruthTable( + Map( + BitPat("b000") -> BitPat("b0"), + BitPat("b001") -> BitPat("b?"), + BitPat("b010") -> BitPat("b?"), + BitPat("b011") -> BitPat("b0"), + // BitPat("b100") -> BitPat("b1"), + // BitPat("b101") -> BitPat("b1"), + BitPat("b110") -> BitPat("b0") + // BitPat("b111") -> BitPat("b1") + ), + BitPat("b1") + ) + ) } "caseX" should "pass" in { - minimizerTest(TruthTable( - Map( - BitPat("b000") -> BitPat("b0"), - // BitPat("b001") -> BitPat("b?"), - // BitPat("b010") -> BitPat("b?"), - BitPat("b011") -> BitPat("b0"), - BitPat("b100") -> BitPat("b1"), - BitPat("b101") -> BitPat("b1"), - BitPat("b110") -> BitPat("b0"), - BitPat("b111") -> BitPat("b1") - ), - BitPat("b?") - )) + minimizerTest( + TruthTable( + Map( + BitPat("b000") -> BitPat("b0"), + // BitPat("b001") -> BitPat("b?"), + // BitPat("b010") -> BitPat("b?"), + BitPat("b011") -> BitPat("b0"), + BitPat("b100") -> BitPat("b1"), + BitPat("b101") -> BitPat("b1"), + BitPat("b110") -> BitPat("b0"), + BitPat("b111") -> BitPat("b1") + ), + BitPat("b?") + ) + ) } "caseMultiDefault" should "pass" in { - minimizerTest(TruthTable( - Map( - BitPat("b000") -> BitPat("b0100"), - BitPat("b001") -> BitPat("b?111"), - BitPat("b010") -> BitPat("b?000"), - BitPat("b011") -> BitPat("b0101"), - BitPat("b111") -> BitPat("b1101") - ), - BitPat("b?100") - )) + minimizerTest( + TruthTable( + Map( + BitPat("b000") -> BitPat("b0100"), + BitPat("b001") -> BitPat("b?111"), + BitPat("b010") -> BitPat("b?000"), + BitPat("b011") -> BitPat("b0101"), + BitPat("b111") -> BitPat("b1101") + ), + BitPat("b?100") + ) + ) } "case7SegDecoder" should "pass" in { - minimizerTest(TruthTable( - Map( - BitPat("b0000") -> BitPat("b111111001"), - BitPat("b0001") -> BitPat("b011000001"), - BitPat("b0010") -> BitPat("b110110101"), - BitPat("b0011") -> BitPat("b111100101"), - BitPat("b0100") -> BitPat("b011001101"), - BitPat("b0101") -> BitPat("b101101101"), - BitPat("b0110") -> BitPat("b101111101"), - BitPat("b0111") -> BitPat("b111000001"), - BitPat("b1000") -> BitPat("b111111101"), - BitPat("b1001") -> BitPat("b111101101"), - ), - BitPat("b???????10") - )) + minimizerTest( + TruthTable( + Map( + BitPat("b0000") -> BitPat("b111111001"), + BitPat("b0001") -> BitPat("b011000001"), + BitPat("b0010") -> BitPat("b110110101"), + BitPat("b0011") -> BitPat("b111100101"), + BitPat("b0100") -> BitPat("b011001101"), + BitPat("b0101") -> BitPat("b101101101"), + BitPat("b0110") -> BitPat("b101111101"), + BitPat("b0111") -> BitPat("b111000001"), + BitPat("b1000") -> BitPat("b111111101"), + BitPat("b1001") -> BitPat("b111101101") + ), + BitPat("b???????10") + ) + ) } // A simple RV32I decode table example @@ -217,6 +227,7 @@ trait MinimizerSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { val FN_SLTU = "1110" val FN_SGEU = "1111" + // format: off minimizerTest(TruthTable( Map( BNE -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SNE, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N), @@ -271,40 +282,44 @@ trait MinimizerSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { ).map { case (k, v) => BitPat(s"b$k") -> BitPat(s"b${v.reduce(_ + _)}") }, BitPat(s"b${Seq(N, X, X, X, X, X, X, X, X, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, X, X, X, X, X, X, X, CSR_X, X, X, X, X).reduce(_ + _)}") )) + // format: on } "output is 0" should "pass" in { - minimizerTest(TruthTable.fromString( - """00->0 - |01->? - |10->0 - |11->0 - | ? - |""".stripMargin - - )) + minimizerTest( + TruthTable.fromString( + """00->0 + |01->? + |10->0 + |11->0 + | ? + |""".stripMargin + ) + ) } "output is 1" should "pass" in { - minimizerTest(TruthTable.fromString( - """00->1 - |01->? - |10->1 - |11->1 - | ? - |""".stripMargin - - )) + minimizerTest( + TruthTable.fromString( + """00->1 + |01->? + |10->1 + |11->1 + | ? + |""".stripMargin + ) + ) } // I know this seems to be crazy, but if user is crazy as well... "output is dont care" should "pass" in { - minimizerTest(TruthTable.fromString( - """00->? - |01->? - |10->? - |11->? - | ? - |""".stripMargin - - )) + minimizerTest( + TruthTable.fromString( + """00->? + |01->? + |10->? + |11->? + | ? + |""".stripMargin + ) + ) } } |