6 files changed, 36 insertions, 43 deletions
diff --git a/docs/src/cookbooks/naming.md b/docs/src/cookbooks/naming.md
index 098ea898..a41a1e9a 100644
--- a/docs/src/cookbooks/naming.md
+++ b/docs/src/cookbooks/naming.md
@@ -48,7 +48,7 @@ Use the `.suggestName` method, which is on all classes which subtype `Data`.
 You can use the `noPrefix { ... }` to strip the prefix from all signals generated in that scope.
 
 ```scala mdoc
-class ExampleNoPrefix extends MultiIOModule {
+class ExampleNoPrefix extends Module {
   val in = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt()))
 
@@ -68,14 +68,14 @@ In cases where a FIRRTL transform renames a signal/instance, you can use the `fo
 ```scala mdoc
 import chisel3.util.experimental.{forceName, InlineInstance}
 
-class WrapperExample extends MultiIOModule {
+class WrapperExample extends Module {
   val in = IO(Input(UInt(3.W)))
   val out = IO(Output(UInt(3.W)))
   val inst = Module(new Wrapper)
   inst.in := in
   out := inst.out
 }
-class Wrapper extends MultiIOModule with InlineInstance {
+class Wrapper extends Module with InlineInstance {
   val in = IO(Input(UInt(3.W)))
   val out = IO(Output(UInt(3.W)))
   val inst = Module(new MyLeaf)
@@ -83,7 +83,7 @@ class Wrapper extends MultiIOModule with InlineInstance {
   inst.in := in
   out := inst.out
 }
-class MyLeaf extends MultiIOModule {
+class MyLeaf extends Module {
   val in = IO(Input(UInt(3.W)))
   val out = IO(Output(UInt(3.W)))
   out := in
diff --git a/docs/src/explanations/naming.md b/docs/src/explanations/naming.md
index fb1121f9..60c653aa 100644
--- a/docs/src/explanations/naming.md
+++ b/docs/src/explanations/naming.md
@@ -44,7 +44,7 @@ class MyBundle extends Bundle {
   val foo = Input(UInt(3.W))
   // val foo = autoNameRecursively("foo")(Input(UInt(3.W)))
 }
-class Example1 extends MultiIOModule {
+class Example1 extends Module {
   val io = IO(new MyBundle())
   // val io = autoNameRecursively("io")(IO(new MyBundle()))
 }
@@ -57,7 +57,7 @@ Otherwise, it is rewritten to also include the name as a prefix to any signals g
 side of the val declaration:
 
 ```scala mdoc
-class Example2 extends MultiIOModule {
+class Example2 extends Module {
   val in = IO(Input(UInt(2.W)))
   // val in = autoNameRecursively("in")(prefix("in")(IO(Input(UInt(2.W)))))
 
@@ -80,7 +80,7 @@ ChiselStage.emitVerilog(new Example2)
 Note that the naming also works if the hardware type is nested in an `Option` or a subtype of `Iterable`:
 
 ```scala mdoc
-class Example3 extends MultiIOModule {
+class Example3 extends Module {
   val in = IO(Input(UInt(2.W)))
   // val in = autoNameRecursively("in")(prefix("in")(IO(Input(UInt(2.W)))))
 
@@ -102,7 +102,7 @@ ChiselStage.emitVerilog(new Example3)
 
 There is also a slight variant (`autoNameRecursivelyProduct`) for naming hardware with names provided by an unapply:
 ```scala mdoc
-class UnapplyExample extends MultiIOModule {
+class UnapplyExample extends Module {
   def mkIO() = (IO(Input(UInt(2.W))), IO(Output(UInt())))
   val (in, out) = mkIO()
   // val (in, out) = autoNameRecursivelyProduct(List(Some("in"), Some("out")))(mkIO())
@@ -126,7 +126,7 @@ but don't want to influence other names in the module.
 In the following example, we prefix additional logic with "ECO", where `Example4` is pre-ECO and `Example5` is post-ECO:
 
 ```scala mdoc
-class Example4 extends MultiIOModule {
+class Example4 extends Module {
   val in = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt()))
 
@@ -135,7 +135,7 @@ class Example4 extends MultiIOModule {
   out := add + 1.U
 }
 
-class Example5 extends MultiIOModule {
+class Example5 extends Module {
   val in = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt()))
 
@@ -152,7 +152,7 @@ ChiselStage.emitVerilog(new Example5)
 Also note that the prefixes append to each other (including the prefix generated by the compiler plugin):
 
 ```scala mdoc
-class Example6 extends MultiIOModule {
+class Example6 extends Module {
   val in = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt()))
 
@@ -169,7 +169,7 @@ Sometimes you may want to disable the prefixing. This might occur if you are wri
 don't want the prefixing behavior. In this case, you can use the `noPrefix` object:
 
 ```scala mdoc
-class Example7 extends MultiIOModule {
+class Example7 extends Module {
   val in = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt()))
 
@@ -188,7 +188,7 @@ If you want to specify the name of a signal, you can always use the `.suggestNam
 name will still be prefixed (including by the plugin). You can always use the `noPrefix` object to strip this.
 
 ```scala mdoc
-class Example8 extends MultiIOModule {
+class Example8 extends Module {
   val in = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt()))
 
@@ -208,7 +208,7 @@ value. Note that you can parameterize the name by the module's parameters. This
 names more stable and is highly recommended to do.
 
 ```scala mdoc
-class Example9(width: Int) extends MultiIOModule {
+class Example9(width: Int) extends Module {
   override val desiredName = s"EXAMPLE9WITHWIDTH$width"
   val in = IO(Input(UInt(width.W)))
   val out = IO(Output(UInt()))
@@ -236,7 +236,7 @@ For example, the signals in the following module are in a nested scope; the plug
 reflection naming cannot:
 
 ```scala mdoc
-class Example10 extends MultiIOModule {
+class Example10 extends Module {
   {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt()))
diff --git a/docs/src/wiki-deprecated/cookbook.md b/docs/src/wiki-deprecated/cookbook.md
index 7fa97579..9a10a689 100644
--- a/docs/src/wiki-deprecated/cookbook.md
+++ b/docs/src/wiki-deprecated/cookbook.md
@@ -282,12 +282,12 @@ class ModuleWithOptionalIOs(flag: Boolean) extends Module {
 }
 ```
 
-The following is an example for a `MultiIOModule` where an entire `IO` is optional:
+The following is an example where an entire `IO` is optional:
 
 ```scala mdoc:silent:reset
 import chisel3._
 
-class ModuleWithOptionalIO(flag: Boolean) extends MultiIOModule {
+class ModuleWithOptionalIO(flag: Boolean) extends Module {
   val in = if (flag) Some(IO(Input(Bool()))) else None
   val out = IO(Output(Bool()))
 
diff --git a/docs/src/wiki-deprecated/modules.md b/docs/src/wiki-deprecated/modules.md
index 1d85b88e..23006c9c 100644
--- a/docs/src/wiki-deprecated/modules.md
+++ b/docs/src/wiki-deprecated/modules.md
@@ -10,8 +10,8 @@ The hierarchical module namespace is accessible in downstream tools
 to aid in debugging and physical layout.  A user-defined module is
 defined as a *class* which:
 
- - inherits from ```Module```,
- - contains an interface wrapped in a Module's ```IO()``` method and stored in a port field named ```io```, and
+ - inherits from `Module`,
+ - contains at least one interface wrapped in a Module's `IO()` method (traditionally stored in a port field named ```io```), and
  - wires together subcircuits in its constructor.
 
 As an example, consider defining your own two-input multiplexer as a
@@ -86,24 +86,18 @@ new object.  We then wire them up to one another and to the ports of
 the ```Mux4``` interface.
 
 Note: Chisel `Module`s have an implicit clock (called `clock`) and
-an implicit reset (called `reset`). For different behavior, Chisel
-provides both `MultiIOModule` and `RawModule`.
+an implicit reset (called `reset`). To create modules without implicit
+clock and reset, Chisel provides `RawModule`.
 
-### `MultiIOModule`
-
-A `MultiIOModule` allows you to define as many different `IO` as needed
-and does not require you to implement an abstract member `io`.
-This can be useful when programmatically adding `IO` or adding `IO` via inheritance.
-An artifact of this is that Verilog generated from a `MultiIOModule` will
-*not* have the `io_` prefix. `MultiIOModule`s still have an implicit
-clock and reset like `Module`.
-
-<!-- TODO: Some example -->
+> Historical Note: Prior to Chisel 3.5, Modules were restricted to only
+having a single user-defined port named `io`. There was also a type called
+`MultiIOModule` that provided implicit clock and reset while allowing the
+user to define as many ports as they want. This is now the functionality
+of `Module`.
 
 ### `RawModule`
 
-A `RawModule` is a module that allows you to define as much `IO` as needed
-(like `MultiIOModule`) but **does not provide an implicit clock and reset.**
+A `RawModule` is a module that **does not provide an implicit clock and reset.**
 This can be useful when interfacing a Chisel module with a design that expects
 a specific naming convention for clock or reset.
 
diff --git a/docs/src/wiki-deprecated/ports.md b/docs/src/wiki-deprecated/ports.md
index f8c30b7a..251ce243 100644
--- a/docs/src/wiki-deprecated/ports.md
+++ b/docs/src/wiki-deprecated/ports.md
@@ -30,21 +30,20 @@ provide powerful wiring constructs described later.
 
 (Chisel 3.2+)
 
-Chisel 3.2+ introduces an API `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module, including MultiIOModules, RawModules, and BlackBoxes.
-
+Chisel 3.2 introduced `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module (this includes modules in both `import chisel3._` and `import Chisel._`, as well as BlackBoxes from each package).
 Here is an example of how to use this API:
 
 ```scala
 import chisel3.experimental.DataMirror
 
-class Adder extends MultiIOModule {
+class Adder extends Module {
   val a = IO(Input(UInt(8.W)))
   val b = IO(Input(UInt(8.W)))
   val c = IO(Output(UInt(8.W)))
   c := a +& b
 }
 
-class Test extends MultiIOModule {
+class Test extends Module {
   val adder = Module(new Adder)
   // for debug only
   adder.a := DontCare
diff --git a/docs/src/wiki-deprecated/reset.md b/docs/src/wiki-deprecated/reset.md
index 3aafeccd..f5e4a24a 100644
--- a/docs/src/wiki-deprecated/reset.md
+++ b/docs/src/wiki-deprecated/reset.md
@@ -7,7 +7,7 @@ section: "chisel3"
 ```scala mdoc:invisible
 import chisel3._
 
-class Submodule extends MultiIOModule
+class Submodule extends Module
 ```
 
 As of Chisel 3.2.0, Chisel 3 supports both synchronous and asynchronous reset,
@@ -60,13 +60,13 @@ rather than relying on _Reset Inference_, you can mixin one of the following tra
 For example:
 
 ```scala mdoc:silent
-class MyAlwaysSyncResetModule extends MultiIOModule with RequireSyncReset {
+class MyAlwaysSyncResetModule extends Module with RequireSyncReset {
   val mySyncResetReg = RegInit(false.B) // reset is of type Bool
 }
 ```
 
 ```scala mdoc:silent
-class MyAlwaysAsyncResetModule extends MultiIOModule with RequireAsyncReset {
+class MyAlwaysAsyncResetModule extends Module with RequireAsyncReset {
   val myAsyncResetReg = RegInit(false.B) // reset is of type AsyncReset
 }
 ```
@@ -123,7 +123,7 @@ See ["Multiple Clock Domains"](../explanations/multi-clock) for more information
 The following will make `myReg` as well as both `resetAgnosticReg`s synchronously reset:
 
 ```scala mdoc:silent
-class ForcedSyncReset extends MultiIOModule {
+class ForcedSyncReset extends Module {
   // withReset's argument becomes the implicit reset in its scope
   withReset (reset.asBool) {
     val myReg = RegInit(0.U)
@@ -140,7 +140,7 @@ class ForcedSyncReset extends MultiIOModule {
 The following will make `myReg` as well as both `resetAgnosticReg`s asynchronously reset:
 
 ```scala mdoc:silent
-class ForcedAysncReset extends MultiIOModule {
+class ForcedAysncReset extends Module {
   // withReset's argument becomes the implicit reset in its scope
   withReset (reset.asAsyncReset){
     val myReg = RegInit(0.U)
@@ -164,7 +164,7 @@ It is **not** legal to override the reset type using last-connect semantics
 unless you are overriding a `DontCare`:
 
 ```scala mdoc:silent
-class MyModule extends MultiIOModule {
+class MyModule extends Module {
   val resetBool = Wire(Reset())
   resetBool := DontCare
   resetBool := false.B // this is fine