1 files changed, 11 insertions, 14 deletions
diff --git a/docs/src/explanations/memories.md b/docs/src/explanations/memories.md
index 1f2f83be..10759f25 100644
--- a/docs/src/explanations/memories.md
+++ b/docs/src/explanations/memories.md
@@ -11,35 +11,32 @@ Chisel provides facilities for creating both read only and read/write memories.
 ## ROM
 
 Users can define read-only memories by constructing a `Vec` with `VecInit`.
-`VecInit` can except either a variable-argument number of `Data` literals or a `Seq[Data]` literals that initialize the ROM.
-
-```scala mdoc:invisible
-import chisel3._
-// This is bad, don't do this, use a val
-def counter = util.Counter(true.B, 4)._1
-val Pi = 3.14
-def sin(t: Double): Double = t // What should this be?
-```
+`VecInit` can accept either a variable-argument number of `Data` literals or a `Seq[Data]` literals that initialize the ROM.
 
 For example, users can create a small ROM initialized to 1, 2, 4, 8 and loop through all values using a counter as an address generator as follows:
 
 ```scala mdoc:compile-only
+import chisel3._
+import chisel3.util.Counter
 val m = VecInit(1.U, 2.U, 4.U, 8.U)
-val r = m(counter(m.length.U))
+val c = Counter(m.length)
+c.inc()
+val r = m(c.value)
 ```
 
-We can create an *n* value sine lookup table using a ROM initialized as follows:
+We can create an *n* value sine lookup table generator using a ROM initialized as follows:
 
 ```scala mdoc:compile-only
+import chisel3._
+
+val Pi = math.Pi
 def sinTable(amp: Double, n: Int) = {
   val times =
     (0 until n).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
   val inits =
-    times.map(t => Math.round(amp * sin(t)).asSInt(32.W))
+    times.map(t => Math.round(amp * math.sin(t)).asSInt(32.W))
   VecInit(inits)
 }
-def sinWave(amp: Double, n: Int) =
-  sinTable(amp, n)(counter(n.U))
 ```
 
 where `amp` is used to scale the fixpoint values stored in the ROM.