2 files changed, 49 insertions, 4 deletions
diff --git a/docs/src/appendix/experimental-features.md b/docs/src/appendix/experimental-features.md
index eb91c190..a85704c2 100644
--- a/docs/src/appendix/experimental-features.md
+++ b/docs/src/appendix/experimental-features.md
@@ -10,6 +10,7 @@ Chisel has a number of new features that are worth checking out.  This page is a
 - [FixedPoint](#fixed-point)
 - [Module Variants](#module-variants)
 - [Bundle Literals](#bundle-literals)
+- [Vec Literals](#vec-literals)
 - [Interval Type](#interval-type)
 - [Loading Memories for simulation or FPGA initialization](#loading-memories)
 
@@ -52,7 +53,10 @@ class Example extends RawModule {
 chisel3.stage.ChiselStage.emitVerilog(new Example)
 ```
 
-Partial specification is allowed, defaulting any unconnected fields to 0 (regardless of type).
+Partial specification is allowed, which results in "invalidated fields" as
+described in [Unconnected Wires](../explanations/unconnected-wires).
+Note that this can be used with `RegInit` to construct partially reset registers as
+described in the [Cookbook](../cookbooks/cookbook#how-do-i-partially-reset-an-aggregate-reg).
 
 ```scala mdoc
 class Example2 extends RawModule {
@@ -122,9 +126,10 @@ chisel3.stage.ChiselStage.emitVerilog(new VecExample1a)
 ```
 
 The following examples all use the explicit form.
-With the explicit form partial specification is allowed.
-When used with as a `Reg` `reset` value, only specified indices of the `Reg`'s `Vec`
-will be reset
+With the explicit form partial specification is allowed, which results in
+"invalidated fields" as described in [Unconnected Wires](../explanations/unconnected-wires).
+Note that this can be used with `RegInit` to construct partially reset registers as
+described in the [Cookbook](../cookbooks/cookbook#how-do-i-partially-reset-an-aggregate-reg).
 
 ```scala mdoc
 class VecExample2 extends RawModule {
diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md
index b9e5db38..ab8e76d3 100644
--- a/docs/src/cookbooks/cookbook.md
+++ b/docs/src/cookbooks/cookbook.md
@@ -20,6 +20,7 @@ Please note that these examples make use of [Chisel's scala-style printing](../e
   * [Can I make a 2D or 3D Vector?](#can-i-make-a-2D-or-3D-Vector)
   * [How do I create a Vector of Registers?](#how-do-i-create-a-vector-of-registers)
   * [How do I create a Reg of type Vec?](#how-do-i-create-a-reg-of-type-vec)
+  * [How do I partially reset an Aggregate Reg?](#how-do-i-partially-reset-an-aggregate-reg)
 * Bundles
   * [How do I deal with aliased Bundle fields?](#aliased-bundle-fields)
 * [How do I create a finite state machine?](#how-do-i-create-a-finite-state-machine-fsm)
@@ -234,6 +235,45 @@ class Foo extends RawModule {
 }
 ```
 
+
+### How do I partially reset an Aggregate Reg?
+
+The easiest way is to use a partially-specified [Bundle Literal](#../appendix/experimental-features#bundle-literals)
+or [Vec Literal](#../appendix/experimental-features#vec-literals) to match the type of the Reg.
+
+```scala mdoc:silent:reset
+import chisel3._
+import chisel3.experimental.BundleLiterals._
+
+class MyBundle extends Bundle {
+  val foo = UInt(8.W)
+  val bar = UInt(8.W)
+}
+
+class MyModule extends Module {
+  // Only .foo will be reset, .bar will have no reset value
+  val reg = RegInit((new MyBundle).Lit(_.foo -> 123.U))
+}
+```
+
+If your initial value is not a literal, or if you just prefer, you can use a
+Wire as the initial value for the Reg. Simply connect fields to `DontCare` that
+you do not wish to be reset.
+
+```scala mdoc:silent
+class MyModule2 extends Module {
+  val reg = RegInit({
+    // The wire could be constructed before the reg rather than in the RegInit scope,
+    // but this style has nice lexical scoping behavior, keeping the Wire private
+    val init = Wire(new MyBundle)
+    init := DontCare // No fields will be reset
+    init.foo := 123.U // Last connect override, .foo is reset
+    init
+  })
+}
+```
+
+
 ## Bundles
 
 ### <a name="aliased-bundle-fields"></a> How do I deal with aliased Bundle fields?