summaryrefslogtreecommitdiff
path: root/docs/src
diff options
context:
space:
mode:
Diffstat (limited to 'docs/src')
-rw-r--r--docs/src/cookbooks/cookbook.md3
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md
index e23b158c..d4cf3030 100644
--- a/docs/src/cookbooks/cookbook.md
+++ b/docs/src/cookbooks/cookbook.md
@@ -431,6 +431,9 @@ Unlike `Vecs` which represent a singular Chisel type and must have the same widt
```scala mdoc:verilog
chisel3.stage.ChiselStage.emitVerilog(new CountBits(4))
+ // remove the body of the module by removing everything after ');'
+ .split("\\);")
+ .head + ");\n"
```
## Predictable Naming