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Diffstat (limited to 'docs/src')
| -rw-r--r-- | docs/src/explanations/interfaces-and-connections.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/src/explanations/interfaces-and-connections.md b/docs/src/explanations/interfaces-and-connections.md index 0fb8bae8..5d9cfd3c 100644 --- a/docs/src/explanations/interfaces-and-connections.md +++ b/docs/src/explanations/interfaces-and-connections.md @@ -150,7 +150,7 @@ Below we can see the resulting error for this example: ```scala mdoc:crash ChiselStage.emitVerilog(new BlockWithTemporaryWires) ``` -For more details and information, see [Deep Dive into Connection Operators](connection-operators.md) +For more details and information, see [Deep Dive into Connection Operators](connection-operators) NOTE: When using `Chisel._` (compatibility mode) instead of `chisel3._`, the `:=` operator works in a bidirectional fashion similar to `<>`, but not exactly the same. |