1 files changed, 75 insertions, 6 deletions
diff --git a/docs/src/explanations/interfaces-and-connections.md b/docs/src/explanations/interfaces-and-connections.md
index 9f48b642..0fb8bae8 100644
--- a/docs/src/explanations/interfaces-and-connections.md
+++ b/docs/src/explanations/interfaces-and-connections.md
@@ -4,7 +4,7 @@ title:  "Interfaces and Connections"
 section: "chisel3"
 ---
 
-# Interfaces & Bulk Connections
+# Interfaces & Connections
 
 For more sophisticated modules it is often useful to define and instantiate interface classes while defining the IO for a module. First and foremost, interface classes promote reuse allowing users to capture once and for all common interfaces in a useful form.
 
@@ -18,6 +18,7 @@ As we saw earlier, users can define their own interfaces by defining a class tha
 
 ```scala mdoc:invisible
 import chisel3._
+import chisel3.stage.ChiselStage
 ```
 
 ```scala mdoc:silent
@@ -67,8 +68,34 @@ class CrossbarIo(n: Int) extends Bundle {
 where Vec takes a size as the first argument and a block returning a port as the second argument.
 
 ## Bulk Connections
+Once we have a defined Interface, we can connect to it via a [`MonoConnect`](https://www.chisel-lang.org/api/latest/chisel3/Data.html#:=) operator (`:=`) or [`BiConnect`](https://www.chisel-lang.org/api/latest/chisel3/Data.html#%3C%3E) operator (`<>`).
 
-We can now compose two filters into a filter block as follows:
+### `MonoConnect` Algorithm
+`MonoConnect.connect`, or `:=`, executes a mono-directional connection element-wise.
+
+Note that this isn't commutative. There is an explicit source and sink
+already determined before this function is called.
+
+The connect operation will recurse down the left Data (with the right Data).
+An exception will be thrown if a movement through the left cannot be matched
+in the right. The right side is allowed to have extra fields.
+Vecs must still be exactly the same size.
+
+Note that the LHS element must be writable so, one of these must hold:
+- Is an internal writable node (`Reg` or `Wire`)
+- Is an output of the current module
+- Is an input of a submodule of the current module
+
+Note that the RHS element must be readable so, one of these must hold:
+- Is an internal readable node (`Reg`, `Wire`, `Op`)
+- Is a literal
+- Is a port of the current module or submodule of the current module
+
+
+### `BiConnect` Algorithm
+`BiConnect.connect`, or `<>`, executes a bidirectional connection element-wise. Note that the arguments are left and right (not source and sink) so the intent is for the operation to be commutative. The connect operation will recurse down the left `Data` (with the right `Data`). An exception will be thrown if a movement through the left cannot be matched in the right, or if the right side has extra fields.
+
+Using the biconnect `<>` operator, we can now compose two filters into a filter block as follows:
 ```scala mdoc:silent
 class Block extends Module {
   val io = IO(new FilterIO)
@@ -79,11 +106,53 @@ class Block extends Module {
   f2.io.y <> io.y
 }
 ```
-where <> bulk connects interfaces of opposite gender between sibling modules or interfaces of the same gender between parent/child modules.
 
-Bulk connections connect leaf ports of the same name to each other. If the names do not match or are missing, Chisel does not generate a connection.
+The bidirectional bulk connection operator `<>` connects leaf ports of the same name to each other. The Scala types of the Bundles are not required to match. If one named signal is missing from either side, Chisel will give an error such as in the following example:
+
+```scala mdoc:silent
+
+class NotReallyAFilterIO extends Bundle {
+  val x = Flipped(new PLink)
+  val y = new PLink
+  val z = Output(new Bool())
+}
+class Block2 extends Module {
+  val io1 = IO(new FilterIO)
+  val io2 = IO(Flipped(new NotReallyAFilterIO))
+
+  io1 <> io2
+}
+```
+Below we can see the resulting error for this example:
+```scala mdoc:crash
+ChiselStage.emitVerilog(new Block2)
+```
+Bidirectional connections should only be used with **directioned elements** (like IOs), e.g. connecting two wires isn't supported since Chisel can't necessarily figure out the directions automatically.
+For example, putting two temporary wires and connecting them here will not work, even though the directions could be known from the endpoints:
+
+```scala mdoc:silent
+
+class BlockWithTemporaryWires extends Module {
+  val io = IO(new FilterIO)
+  val f1 = Module(new Filter)
+  val f2 = Module(new Filter)
+  f1.io.x <> io.x
+ val tmp1 = Wire(new FilterIO)
+ val tmp2 = Wire(new FilterIO)
+  f1.io.y <> tmp1
+  tmp1 <> tmp2
+  tmp2 <> f2.io.x
+  f2.io.y <> io.y
+}
+
+```
+Below we can see the resulting error for this example:
+```scala mdoc:crash
+ChiselStage.emitVerilog(new BlockWithTemporaryWires)
+```
+For more details and information, see [Deep Dive into Connection Operators](connection-operators.md)
 
-Caution: bulk connections should only be used with **directioned elements** (like IOs), and is not magical (e.g. connecting two wires isn't supported since Chisel can't necessarily figure out the directions automatically [chisel3#603](https://github.com/freechipsproject/chisel3/issues/603)).
+NOTE: When using `Chisel._` (compatibility mode) instead of `chisel3._`, the `:=` operator works in a bidirectional fashion similar to `<>`, but not exactly the same.
 
 ## The standard ready-valid interface (ReadyValidIO / Decoupled)
 
@@ -144,6 +213,6 @@ class ConsumingData extends Module {
 That means `ready` and `valid` can also be deasserted without a data transfer.
 
 `IrrevocableIO` is a ready-valid interface with the *convention* that the value of `bits` will not change while `valid` is asserted and `ready` is deasserted.
-Also the consumer shall keep `ready` asserted after a cycle where `ready` was high and `valid` was low.
+Also, the consumer shall keep `ready` asserted after a cycle where `ready` was high and `valid` was low.
 Note that the *irrevocable* constraint *is only a convention* and cannot be enforced by the interface.
 Chisel does not automatically generate checkers or assertions to enforce the *irrevocable* convention.