diff options
Diffstat (limited to 'docs/src/explanations/annotations.md')
| -rw-r--r-- | docs/src/explanations/annotations.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/docs/src/explanations/annotations.md b/docs/src/explanations/annotations.md index 19d24605..510ebca5 100644 --- a/docs/src/explanations/annotations.md +++ b/docs/src/explanations/annotations.md @@ -4,6 +4,8 @@ title: "Annotations" section: "chisel3" --- +# Annotations + `Annotation`s are metadata containers associated with zero or more "things" in a FIRRTL circuit. Commonly, `Annotation`s are used to communicate information from Chisel to a specific, custom FIRRTL `Transform`. In this way `Annotation`s can be viewed as the "arguments" that a specific `Transform` consumes. @@ -132,10 +134,8 @@ class ModC(widthC: Int) extends Module { Compiling this circuit to Verilog will then result in the `InfoTransform` running and the added `println`s showing information about the components annotated. -```scala mdoc +```scala mdoc:compile-only import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation} -// This currently doesn't work because of mdoc limitations. However, it will work -// in your normal Scala code. -//(new ChiselStage).execute(Array.empty, Seq(ChiselGeneratorAnnotation(() => new ModC(4)))) +(new ChiselStage).execute(Array.empty, Seq(ChiselGeneratorAnnotation(() => new ModC(4)))) ``` |