diff options
Diffstat (limited to 'core')
| -rw-r--r-- | core/src/main/scala/chisel3/SeqUtils.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala index 64904e51..e263810a 100644 --- a/core/src/main/scala/chisel3/SeqUtils.scala +++ b/core/src/main/scala/chisel3/SeqUtils.scala @@ -15,12 +15,15 @@ private[chisel3] object SeqUtils { * in the sequence forms the most significant bits. * * Equivalent to r(n-1) ## ... ## r(1) ## r(0). + * @note This returns a `0.U` if applied to a zero-element `Vec`. */ def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg /** @group SourceInfoTransformMacros */ def do_asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { - if (in.tail.isEmpty) { + if (in.isEmpty) { + 0.U + } else if (in.tail.isEmpty) { in.head.asUInt } else { val left = prefix("left") { |