1 files changed, 14 insertions, 13 deletions
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
index 4b7c0815..3f37308c 100644
--- a/core/src/main/scala/chisel3/Mem.scala
+++ b/core/src/main/scala/chisel3/Mem.scala
@@ -9,7 +9,7 @@ import firrtl.{ir => fir}
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.{MemTransform, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo}
+import chisel3.internal.sourceinfo.{MemTransform, SourceInfo, SourceInfoTransform, SourceLine, UnlocatableSourceInfo}
 
 object Mem {
 
@@ -57,6 +57,16 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
   _parent.foreach(_.addId(this))
 
   private val clockInst: Clock = Builder.forcedClock
+
+  protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = {
+    // Turn into pretty String if possible, if not, Builder.deprecated will find one via stack trace
+    val infoStr = sourceInfo.collect { case SourceLine(file, line, col) => s"$file:$line:$col" }
+    Builder.deprecated(
+      "The clock used to initialize the memory is different than the one used to initialize the port. " +
+        "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0",
+      infoStr
+    )
+  }
   // REVIEW TODO: make accessors (static/dynamic, read/write) combinations consistent.
 
   /** Creates a read accessor into the memory with static addressing. See the
@@ -123,10 +133,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     compileOptions:      CompileOptions
   ): T = {
     if (warn && clock != clockInst) {
-      Builder.warning(
-        "The clock used to initialize the memory is different than the one used to initialize the port. " +
-          "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0"
-      )
+      clockWarning(Some(sourceInfo))
     }
     makePort(sourceInfo, idx, dir, clock)
   }
@@ -158,10 +165,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     implicit compileOptions: CompileOptions
   ): Unit = {
     if (warn && clock != clockInst) {
-      Builder.warning(
-        "The clock used to initialize the memory is different than the one used to initialize the port. " +
-          "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0"
-      )
+      clockWarning(None)
     }
     implicit val sourceInfo = UnlocatableSourceInfo
     makePort(UnlocatableSourceInfo, idx, MemPortDirection.WRITE, clock) := data
@@ -220,10 +224,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
   ): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
     if (warn && clock != clockInst) {
-      Builder.warning(
-        "The clock used to initialize the memory is different than the one used to initialize the port. " +
-          "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0"
-      )
+      clockWarning(None)
     }
     val accessor = makePort(sourceInfo, idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]]
     val dataVec = data.asInstanceOf[Vec[Data]]