diff options
Diffstat (limited to 'core')
| -rw-r--r-- | core/src/main/scala/chisel3/SeqUtils.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala index 9f068898..97bdc505 100644 --- a/core/src/main/scala/chisel3/SeqUtils.scala +++ b/core/src/main/scala/chisel3/SeqUtils.scala @@ -113,10 +113,17 @@ private[chisel3] object SeqUtils { buildAndOrMultiplexor(sels.zip(inWidthMatched)) } - case _: Aggregate => + case agg: Aggregate => val allDefineWidth = in.forall { case (_, element) => element.widthOption.isDefined } - if(allDefineWidth) { - buildAndOrMultiplexor(in) + if (allDefineWidth) { + val out = Wire(agg) + val (sel, inData) = in.unzip + val inElts = inData.map(_.asInstanceOf[Aggregate].getElements) + // We want to iterate on the columns of inElts, so we transpose + out.getElements.zip(inElts.transpose).foreach { case (outElt, elts) => + outElt := oneHotMux(sel.zip(elts)) + } + out.asInstanceOf[T] } else { throwException(s"Cannot Mux1H with aggregates with inferred widths") |