6 files changed, 34 insertions, 13 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index 2c4f67db..b0be3c24 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -966,7 +966,7 @@ abstract class Record extends Aggregate {
     case _ => false
   }
 
-  private[chisel3] override def _onModuleClose: Unit = {
+  private[chisel3] def _onModuleClose: Unit = {
     // This is usually done during binding, but these must still be set for unbound Records
     if (this.binding.isEmpty) {
       setElementRefs()
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 0b05eb69..0beaa3ef 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -824,6 +824,25 @@ abstract class Data extends HasId with NamedComponent {
 
   /** Default pretty printing */
   def toPrintable: Printable
+
+  implicit class AsReadOnly[T <: Data](self: T) {
+
+    /** Returns a read-only view of this Data
+      *
+      * It is illegal to connect to the return value of this method.
+      * This Data this method is called on must be a hardware type.
+      */
+    def readOnly: T = {
+      val alreadyReadOnly = self.isLit || self.topBindingOpt.exists(_.isInstanceOf[ReadOnlyBinding])
+      if (alreadyReadOnly) {
+        self
+      } else {
+        self
+        // todo fix when adding dataview
+        // self.viewAsReadOnly(_ => "Cannot connect to read-only value")
+      }
+    }
+  }
 }
 
 object Data {
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 212215ab..4db632bf 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -31,16 +31,16 @@ object Module {
     if (Builder.currentModule.isDefined && module._component.isDefined) {
       // Class only uses the Definition API, and is not allowed here.
       module match {
-        case _: Class[_] => throwException("Module() cannot be called on a Class. Please use Definition().")
+        // case _: Class[_] => throwException("Module() cannot be called on a Class. Please use Definition().")
         case _ => ()
       }
 
       val component = module._component.get
       component match {
-        case DefClass(_, name, _, _) =>
-          Builder.referenceUserContainer match {
-            case rm:  RawModule => rm.addCommand(DefObject(module, name))
-          }
+        // case DefClass(_, name, _, _) =>
+        //   Builder.referenceUserContainer match {
+        //     case rm:  RawModule => rm.addCommand(DefObject(module, name))
+        //   }
         case _ => pushCommand(DefInstance(module, component.ports))
       }
       module.initializeInParent()
@@ -169,8 +169,8 @@ abstract class Module extends RawModule {
   final val clock: Clock = IO(Input(Clock())).suggestName("clock")
   final val reset: Reset = IO(Input(mkReset)).suggestName("reset")
 
-  override protected def implicitClock: Clock = clock
-  override protected def implicitReset: Reset = reset
+  protected def implicitClock: Clock = clock
+  protected def implicitReset: Reset = reset
 
   // TODO Delete these
   private var _override_clock: Option[Clock] = None
diff --git a/core/src/main/scala/chisel3/internal/Error.scala b/core/src/main/scala/chisel3/internal/Error.scala
index 730c9510..69042c3f 100644
--- a/core/src/main/scala/chisel3/internal/Error.scala
+++ b/core/src/main/scala/chisel3/internal/Error.scala
@@ -3,8 +3,10 @@
 package chisel3.internal
 
 import scala.annotation.tailrec
-import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
-import scala.util.control.NoStackTrace
+import scala.collection.mutable.{ArrayBuffer, LinkedHashMap, LinkedHashSet}
+import scala.util.Try
+import scala.util.control.{NoStackTrace, NonFatal}
+import scala.util.matching.Regex
 import _root_.logger.Logger
 
 object ExceptionHelpers {
@@ -191,7 +193,7 @@ private[chisel3] class ErrorLog(warningsAsErrors: Boolean) {
   }
 
   private def warn(m: => String, loc: Option[StackTraceElement]): LogEntry =
-    if (warningsAsErrors) new Error(m, loc) else new Warning(m, loc)
+    if (warningsAsErrors) new Error(m, loc) else new Info(m, None)
 
   /** Log a warning message */
   def warning(m: => String): Unit = {
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 9fee727c..81a35ddc 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -342,7 +342,7 @@ case class Circuit(
   ) = Circuit(name, components, annotations, renames, newAnnotations)
 
 }
-case class DefClass(id: Class[_], name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+// case class DefClass(id: Class[?], name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 object Circuit
     extends scala.runtime.AbstractFunction4[String, Seq[Component], Seq[ChiselAnnotation], RenameMap, Circuit] {
   def unapply(c: Circuit): Option[(String, Seq[Component], Seq[ChiselAnnotation], RenameMap)] = {
diff --git a/core/src/main/scala/chisel3/internal/package.scala b/core/src/main/scala/chisel3/internal/package.scala
index 25d9129f..2e1448a5 100644
--- a/core/src/main/scala/chisel3/internal/package.scala
+++ b/core/src/main/scala/chisel3/internal/package.scala
@@ -69,7 +69,7 @@ package object internal {
   private[chisel3] def _padHandleBool[A <: Bits](
     x:     A,
     width: Int
-  )(using Quotes): A = x match {
+  )(using Quotes, quoted.Type[A]): A = x match {
     case b: Bool if !b.isLit && width > 1 && Type.of[A] == Type.of[UInt] =>
       val _pad = Wire(UInt(width.W))
       _pad := b