summaryrefslogtreecommitdiff
path: root/core/src
diff options
context:
space:
mode:
Diffstat (limited to 'core/src')
-rw-r--r--core/src/main/scala/chisel3/SeqUtils.scala10
1 files changed, 5 insertions, 5 deletions
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala
index f6642bcb..da6fc802 100644
--- a/core/src/main/scala/chisel3/SeqUtils.scala
+++ b/core/src/main/scala/chisel3/SeqUtils.scala
@@ -7,7 +7,7 @@ import chisel3.internal.{prefix, throwException}
import scala.language.experimental.macros
import chisel3.internal.sourceinfo._
-
+import chisel3.internal.plugin.autoNameRecursively
private[chisel3] object SeqUtils {
/** Concatenates the data elements of the input sequence, in sequence order, together.
@@ -26,12 +26,12 @@ private[chisel3] object SeqUtils {
} else if (in.tail.isEmpty) {
in.head.asUInt
} else {
- val lo = prefix("lo") {
+ val lo = autoNameRecursively("lo")(prefix("lo") {
asUInt(in.slice(0, in.length/2))
- }.autoSeed("lo")
- val hi = prefix("hi") {
+ })
+ val hi = autoNameRecursively("hi")(prefix("hi") {
asUInt(in.slice(in.length/2, in.length))
- }.autoSeed("hi")
+ })
hi ## lo
}
}