diff options
Diffstat (limited to 'core/src')
27 files changed, 692 insertions, 1102 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index a3a8470f..731d12de 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -10,7 +10,6 @@ import chisel3.experimental.{BaseModule, BundleLiteralException, OpaqueType, Vec import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo._ import java.lang.Math.{floor, log10, pow} import scala.collection.mutable @@ -57,25 +56,12 @@ sealed abstract class Aggregate extends Data { private[chisel3] def width: Width = elementsIterator.map(_.width).foldLeft(0.W)(_ + _) - private[chisel3] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = { - // If the source is a DontCare, generate a DefInvalid for the sink, - // otherwise, issue a Connect. - if (that == DontCare) { - pushCommand(DefInvalid(sourceInfo, Node(this))) - } else { - pushCommand(BulkConnect(sourceInfo, Node(this), Node(that))) - } - } - - override def asUInt(using sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + override def asUInt: UInt = { SeqUtils.asUInt(flatten.map(_.asUInt)) } private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { var i = 0 val bits = if (that.isLit) that else WireDefault(UInt(this.width), that) // handles width padding @@ -95,15 +81,11 @@ sealed abstract class Aggregate extends Data { } object Vec { - /** Creates a new [[Vec]] with `n` entries of the specified data type. * * @note elements are NOT assigned by default and have no value */ - def apply[T <: Data](n: Int, gen: T)(using sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { - if (compileOptions.declaredTypeMustBeUnbound) { - requireIsChiselType(gen, "vec type") - } + def apply[T <: Data](n: Int, gen: T): Vec[T] = { new Vec(gen.cloneTypeFull, n) } @@ -146,7 +128,7 @@ object Vec { * - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined) * - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier */ -sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extends Aggregate { +sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extends Aggregate with Iterator[T] { override def toString: String = { topBindingOpt match { @@ -212,7 +194,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend * * @note the length of this Vec must match the length of the input Seq */ - def <>(that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = { + def <>(that: Seq[T]): Unit = { if (this.length != that.length) { Builder.error("Vec and Seq being bulk connected have different lengths!") } @@ -221,14 +203,14 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def <>(that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = + def <>(that: Vec[T]): Unit = this.bulkConnect(that.asInstanceOf[Data]) /** Strong bulk connect, assigning elements in this Vec from elements in a Seq. * * @note the length of this Vec must match the length of the input Seq */ - def :=(that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = { + def :=(that: Seq[T]): Unit = { require( this.length == that.length, s"Cannot assign to a Vec of length ${this.length} from a Seq of different length ${that.length}" @@ -238,11 +220,11 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def :=(that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this.connect(that) + def :=(that: Vec[T]): Unit = this.connect(that) /** Creates a dynamically indexed read or write accessor into the array. */ - def apply(p: UInt)(implicit compileOptions: CompileOptions): T = { + def apply(p: UInt): T = { requireIsHardware(this, "vec") requireIsHardware(p, "vec index") @@ -263,7 +245,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend // Perhaps there's a cleaner way of accomplishing this... port.bind(ChildBinding(this), reconstructedResolvedDirection) - val i = Vec.truncateIndex(p, length)(UnlocatableSourceInfo, compileOptions) + val i = Vec.truncateIndex(p, length) port.setRef(this, i) port @@ -292,55 +274,6 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend PString("Vec(") + Printables(elts) + PString(")") } - /** A reduce operation in a tree like structure instead of sequentially - * @example An adder tree - * {{{ - * val sumOut = inputNums.reduceTree((a: T, b: T) => (a + b)) - * }}} - */ - /** A reduce operation in a tree like structure instead of sequentially - * @example A pipelined adder tree - * {{{ - * val sumOut = inputNums.reduceTree( - * (a: T, b: T) => RegNext(a + b), - * (a: T) => RegNext(a) - * ) - * }}} - */ - def reduceTree( - redOp: (T, T) => T, - layerOp: (T) => T = (x: T) => x - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions - ): T = { - require(!isEmpty, "Cannot apply reduction on a vec of size 0") - - def recReduce[T](s: Seq[T], op: (T, T) => T, lop: (T) => T): T = { - - val n = s.length - n match { - case 1 => lop(s(0)) - case 2 => op(s(0), s(1)) - case _ => - val m = pow(2, floor(log10(n - 1) / log10(2))).toInt // number of nodes in next level, will be a power of 2 - val p = 2 * m - n // number of nodes promoted - - val l = s.take(p).map(lop) - val r = s - .drop(p) - .grouped(2) - .map { - case Seq(a, b) => op(a, b) - } - .toVector - recReduce(l ++ r, op, lop) - } - } - - recReduce(this, redOp, layerOp) - } - /** Creates a Vec literal of this type with specified values. this must be a chisel type. * * @param elementInitializers literal values, specified as a pair of the Vec field to the literal value. @@ -357,9 +290,6 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend */ private[chisel3] def _makeLit( elementInitializers: (Int, T)* - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): this.type = { def checkLiteralConstruction(): Unit = { @@ -518,9 +448,6 @@ object VecInit { */ private def getConnectOpFromDirectionality[T <: Data]( proto: T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): (T, T) => Unit = proto.direction match { case ActualDirection.Input | ActualDirection.Output | ActualDirection.Unspecified => // When internal wires are involved, driver / sink must be specified explicitly, otherwise @@ -542,7 +469,7 @@ object VecInit { * element * @note output elements are connected from the input elements */ - def apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { + def apply[T <: Data](elts: Seq[T]): Vec[T] = { // REVIEW TODO: this should be removed in favor of the apply(elts: T*) // varargs constructor, which is more in line with the style of the Scala // collection API. However, a deprecation phase isn't possible, since @@ -554,7 +481,7 @@ object VecInit { require(elts.nonEmpty, "Vec hardware values are not allowed to be empty") elts.foreach(requireIsHardware(_, "vec element")) - val vec = Wire(Vec(elts.length, cloneSupertype(elts, "Vec"))) + val vec: Vec[T] = Wire(Vec(elts.length, cloneSupertype(elts, "Vec"))) val op = getConnectOpFromDirectionality(vec.head) (vec.zip(elts)).foreach { x => @@ -571,7 +498,7 @@ object VecInit { * element * @note output elements are connected from the input elements */ - def apply[T <: Data](elt0: T, elts: T*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = + def apply[T <: Data](elt0: T, elts: T*): Vec[T] = apply(elt0 +: elts.toSeq) /** Creates a new [[Vec]] of length `n` composed of the results of the given @@ -585,9 +512,6 @@ object VecInit { def tabulate[T <: Data]( n: Int )(gen: (Int) => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Vec[T] = apply((0 until n).map(i => gen(i))) @@ -604,9 +528,6 @@ object VecInit { n: Int, m: Int )(gen: (Int, Int) => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Vec[Vec[T]] = { // TODO make this lazy (requires LazyList and cross compilation, beyond the scope of this PR) val elts = Seq.tabulate(n, m)(gen) @@ -641,9 +562,6 @@ object VecInit { m: Int, p: Int )(gen: (Int, Int, Int) => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Vec[Vec[Vec[T]]] = { // TODO make this lazy (requires LazyList and cross compilation, beyond the scope of this PR) val elts = Seq.tabulate(n, m, p)(gen) @@ -674,7 +592,7 @@ object VecInit { * @param gen function that takes in an element T and returns an output * element of the same type */ - def fill[T <: Data](n: Int)(gen: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = + def fill[T <: Data](n: Int)(gen: => T): Vec[T] = apply(Seq.fill(n)(gen)) /** Creates a new 2D [[Vec]] of length `n by m` composed of the result of the given @@ -689,9 +607,6 @@ object VecInit { n: Int, m: Int )(gen: => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Vec[Vec[T]] = { tabulate(n, m)((_, _) => gen) } @@ -710,9 +625,6 @@ object VecInit { m: Int, p: Int )(gen: => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Vec[Vec[Vec[T]]] = { tabulate(n, m, p)((_, _, _) => gen) } @@ -729,9 +641,6 @@ object VecInit { start: T, len: Int )(f: (T) => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Vec[T] = apply(Seq.iterate(start, len)(f)) @@ -739,7 +648,7 @@ object VecInit { /** A trait for [[Vec]]s containing common hardware generators for collection * operations. */ - def apply[T <: Data](p: UInt)(implicit compileOptions: CompileOptions): T + // def apply[T <: Data](p: UInt): T // IndexedSeq has its own hashCode/equals that we must not use override def hashCode: Int = super[HasId].hashCode @@ -747,23 +656,23 @@ object VecInit { /** Outputs true if p outputs true for every element. */ - def forall[T <: Data](p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = + def forall[T <: Data](p: T => Bool): Bool = (this.map(p)).fold(true.B)(_ && _) /** Outputs true if p outputs true for at least one element. */ - def exists(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = + def exists(p: T => Bool): Bool = (this.map(p)).fold(false.B)(_ || _) /** Outputs true if the vector contains at least one element equal to x (using * the === operator). */ - def contains(x: T)(implicit sourceInfo: SourceInfo, ev: T <:< UInt, compileOptions: CompileOptions): Bool = + def contains(x: T): Bool = this.exists(_ === x) /** Outputs the number of elements for which p is true. */ - def count(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def count(p: T => Bool): UInt = SeqUtils.count(this.map(p)) /** Helper function that appends an index (literal value) to each element, @@ -773,12 +682,12 @@ object VecInit { /** Outputs the index of the first element for which p outputs true. */ - def indexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def indexWhere(p: T => Bool): UInt = SeqUtils.priorityMux(indexWhereHelper(p)) /** Outputs the index of the last element for which p outputs true. */ - def lastIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def lastIndexWhere(p: T => Bool): UInt = SeqUtils.priorityMux(indexWhereHelper(p).reverse) /** Outputs the index of the element for which p outputs true, assuming that @@ -791,7 +700,7 @@ object VecInit { * true is NOT checked (useful in cases where the condition doesn't always * hold, but the results are not used in those cases) */ - def onlyIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def onlyIndexWhere(p: T => Bool): UInt = SeqUtils.oneHotMux(indexWhereHelper(p)) } @@ -800,7 +709,7 @@ object VecInit { * Record should only be extended by libraries and fairly sophisticated generators. * RTL writers should use [[Bundle]]. See [[Record#elements]] for an example. */ -abstract class Record(private[chisel3] implicit val compileOptions: CompileOptions) extends Aggregate { +abstract class Record extends Aggregate { private[chisel3] def _isOpaqueType: Boolean = this match { case maybe: OpaqueType => maybe.opaqueType @@ -1163,7 +1072,7 @@ package experimental { * } * }}} */ -abstract class Bundle(implicit compileOptions: CompileOptions) extends Record with experimental.AutoCloneType { +abstract class Bundle extends Record with experimental.AutoCloneType { assert( _usingPlugin, "The Chisel compiler plugin is now required for compiling Chisel code. " + diff --git a/core/src/main/scala/chisel3/Annotation.scala b/core/src/main/scala/chisel3/Annotation.scala index d133ab8a..0410e1df 100644 --- a/core/src/main/scala/chisel3/Annotation.scala +++ b/core/src/main/scala/chisel3/Annotation.scala @@ -4,7 +4,7 @@ package chisel3.experimental import scala.language.existentials import chisel3.internal.{Builder, InstanceId} -import chisel3.{CompileOptions, Data, RawModule} +import chisel3.{Data, RawModule} import firrtl.Transform import firrtl.annotations._ import firrtl.options.Unserializable @@ -91,7 +91,7 @@ object doNotDedup { * @param module The module to be marked * @return Unmodified signal `module` */ - def apply[T <: RawModule](module: T)(implicit compileOptions: CompileOptions): Unit = { + def apply[T <: RawModule](module: T): Unit = { annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) }) } } diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala index ffcd7c95..ca18f475 100644 --- a/core/src/main/scala/chisel3/Bits.scala +++ b/core/src/main/scala/chisel3/Bits.scala @@ -5,7 +5,6 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushOp import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.firrtl.PrimOp._ import _root_.firrtl.{ir => firrtlir} import _root_.firrtl.{constraint => firrtlconstraint} @@ -15,7 +14,7 @@ import _root_.firrtl.{constraint => firrtlconstraint} * @note This is a workaround because macros cannot override abstract methods. */ private[chisel3] sealed trait ToBoolable extends Element { - def asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool + def asBool: Bool } /** A data type for values represented by a single bitvector. This provides basic bitwise operations. @@ -50,22 +49,22 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @group Bitwise */ - def tail(n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + def tail(n: Int): UInt = { val w = width match { case KnownWidth(x) => require(x >= n, s"Can't tail($n) for width $x < $n") Width(x - n) case UnknownWidth() => Width() } - binop(sourceInfo, UInt(width = w), TailOp, n) + binop(UInt(width = w), TailOp, n) } - def head(n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + def head(n: Int): UInt = { width match { case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n") case UnknownWidth() => } - binop(sourceInfo, UInt(Width(n)), HeadOp, n) + binop(UInt(Width(n)), HeadOp, n) } /** Returns the specified bit on this $coll as a [[Bool]], statically addressed. @@ -74,7 +73,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @return the specified bit */ - final def extract(x: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + final def extract(x: BigInt): Bool = { if (x < 0) { Builder.error(s"Negative bit indices are illegal (got $x)") } @@ -90,7 +89,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi case _ => } - pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x))) + pushOp(DefPrim(Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x))) } } @@ -99,7 +98,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @param x an index * @return the specified bit */ - final def apply(x: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = + final def apply(x: BigInt): Bool = extract(x) /** Returns the specified bit on this $coll as a [[Bool]], statically addressed. @@ -107,7 +106,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @param x an index * @return the specified bit */ - final def apply(x: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = + final def apply(x: Int): Bool = extract(BigInt(x)) /** Returns the specified bit on this wire as a [[Bool]], dynamically addressed. @@ -115,7 +114,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @param x a hardware component whose value will be used for dynamic addressing * @return the specified bit */ - final def extract(x: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + final def extract(x: UInt): Bool = { val theBits = this >> x theBits(0) } @@ -125,7 +124,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @param x a hardware component whose value will be used for dynamic addressing * @return the specified bit */ - final def apply(x: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = + final def apply(x: UInt): Bool = extract(x) /** Returns a subset of bits on this $coll from `hi` to `lo` (inclusive), statically addressed. @@ -139,7 +138,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @param y the low bit * @return a hardware component contain the requested bits */ - final def apply(x: Int, y: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + final def apply(x: Int, y: Int): UInt = { if (x < y || y < 0) { Builder.error(s"Invalid bit range ($x,$y)") } @@ -157,7 +156,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi case _ => } - pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y))) + pushOp(DefPrim(UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y))) } } @@ -173,30 +172,30 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @param y the low bit * @return a hardware component contain the requested bits */ - final def apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + final def apply(x: BigInt, y: BigInt): UInt = apply(castToInt(x, "High index"), castToInt(y, "Low index")) - private[chisel3] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T = { + private[chisel3] def unop[T <: Data](dest: T, op: PrimOp): T = { requireIsHardware(this, "bits operated on") - pushOp(DefPrim(sourceInfo, dest, op, this.ref)) + pushOp(DefPrim(dest, op, this.ref)) } - private[chisel3] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T = { + private[chisel3] def binop[T <: Data](dest: T, op: PrimOp, other: BigInt): T = { requireIsHardware(this, "bits operated on") - pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other))) + pushOp(DefPrim(dest, op, this.ref, ILit(other))) } - private[chisel3] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T = { + private[chisel3] def binop[T <: Data](dest: T, op: PrimOp, other: Bits): T = { requireIsHardware(this, "bits operated on") requireIsHardware(other, "bits operated on") - pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref)) + pushOp(DefPrim(dest, op, this.ref, other.ref)) } - private[chisel3] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool = { + private[chisel3] def compop(op: PrimOp, other: Bits): Bool = { requireIsHardware(this, "bits operated on") requireIsHardware(other, "bits operated on") - pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref)) + pushOp(DefPrim(Bool(), op, this.ref, other.ref)) } - private[chisel3] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool = { + private[chisel3] def redop(op: PrimOp): Bool = { requireIsHardware(this, "bits operated on") - pushOp(DefPrim(sourceInfo, Bool(), op, this.ref)) + pushOp(DefPrim(Bool(), op, this.ref)) } /** Pad operator @@ -207,9 +206,9 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @note For [[SInt]]s only, this will do sign extension. * @group Bitwise */ - def pad(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = this.width match { + def pad(that: Int): this.type = this.width match { case KnownWidth(w) if w >= that => this - case _ => binop(sourceInfo, cloneTypeWidth(this.width.max(Width(that))), PadOp, that) + case _ => binop(cloneTypeWidth(this.width.max(Width(that))), PadOp, that) } /** Bitwise inversion operator @@ -217,7 +216,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @return this $coll with each bit inverted * @group Bitwise */ - def unary_~(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def unary_~(): Bits /** Static left shift operator * @@ -226,7 +225,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * $sumWidthInt * @group Bitwise */ - def <<(that: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def <<(that: BigInt): Bits /** Static left shift operator * @@ -235,7 +234,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * $sumWidthInt * @group Bitwise */ - def <<(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def <<(that: Int): Bits /** Dynamic left shift operator * @@ -244,7 +243,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @note The width of the returned $coll is `width of this + pow(2, width of that) - 1`. * @group Bitwise */ - def <<(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def <<(that: UInt): Bits /** Static right shift operator * @@ -253,7 +252,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * $unchangedWidth * @group Bitwise */ - def >>(that: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def >>(that: BigInt): Bits /** Static right shift operator * @@ -262,7 +261,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * $unchangedWidth * @group Bitwise */ - def >>(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def >>(that: Int): Bits /** Dynamic right shift operator * @@ -272,10 +271,10 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * $unchangedWidth * @group Bitwise */ - def >>(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits + def >>(that: UInt): Bits /** Returns the contents of this wire as a [[scala.collection.Seq]] of [[Bool]]. */ - def asBools(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[Bool] = + def asBools: Seq[Bool] = Seq.tabulate(this.getWidth)(i => this(i)) /** Reinterpret this $coll as an [[SInt]] @@ -283,9 +282,9 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @note The arithmetic value is not preserved if the most-significant bit is set. For example, a [[UInt]] of * width 3 and value 7 (0b111) would become an [[SInt]] of width 3 and value -1. */ - def asSInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt + def asSInt: SInt - final def asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + final def asBool: Bool = { width match { case KnownWidth(1) => this(0) case _ => throwException(s"can't covert ${this.getClass.getSimpleName}$width to Bool") @@ -299,9 +298,9 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * $sumWidth * @group Bitwise */ - def ##(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + def ##(that: Bits): UInt = { val w = this.width + that.width - pushOp(DefPrim(sourceInfo, UInt(w), ConcatOp, this.ref, that.ref)) + pushOp(DefPrim(UInt(w), ConcatOp, this.ref, that.ref)) } /** Default print as [[Decimal]] */ @@ -369,19 +368,19 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @group Arithmetic */ - def unary_-(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = 0.U - this + def unary_-(): UInt = 0.U - this - def unary_-%(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = 0.U -% this + def unary_-%(): UInt = 0.U -% this - override def +(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = this +% that - override def -(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = this -% that - override def /(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width), DivideOp, that) - override def %(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width.min(that.width)), RemOp, that) - override def *(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width + that.width), TimesOp, that) + override def +(that: UInt): UInt = this +% that + override def -(that: UInt): UInt = this -% that + override def /(that: UInt): UInt = + binop(UInt(this.width), DivideOp, that) + override def %(that: UInt): UInt = + binop(UInt(this.width.min(that.width)), RemOp, that) + override def *(that: UInt): UInt = + binop(UInt(this.width + that.width), TimesOp, that) /** Multiplication operator * @@ -391,7 +390,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * $singleCycleMul * @group Arithmetic */ - def *(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = that * this + def *(that: SInt): SInt = that * this /** Addition operator (expanding width) * @@ -425,16 +424,16 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @group Arithmetic */ - def +&(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt((this.width.max(that.width)) + 1), AddOp, that) + def +&(that: UInt): UInt = + binop(UInt((this.width.max(that.width)) + 1), AddOp, that) - def +%(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def +%(that: UInt): UInt = (this +& that).tail(1) - def -&(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def -&(that: UInt): UInt = (this.subtractAsSInt(that)).asUInt - def -%(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def -%(that: UInt): UInt = (this.subtractAsSInt(that)).tail(1) /** Bitwise and operator @@ -461,19 +460,19 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @group Bitwise */ - def abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = this + def abs: UInt = this - def &(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width.max(that.width)), BitAndOp, that) + def &(that: UInt): UInt = + binop(UInt(this.width.max(that.width)), BitAndOp, that) - def |(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width.max(that.width)), BitOrOp, that) + def |(that: UInt): UInt = + binop(UInt(this.width.max(that.width)), BitOrOp, that) - def ^(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width.max(that.width)), BitXorOp, that) + def ^(that: UInt): UInt = + binop(UInt(this.width.max(that.width)), BitXorOp, that) - def unary_~(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - unop(sourceInfo, UInt(width = width), BitNotOp) + def unary_~(): UInt = + unop(UInt(width = width), BitNotOp) // REVIEW TODO: Can these be defined on Bits? /** Or reduction operator @@ -509,20 +508,20 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U "Chisel 3.5" ) - def orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, OrReduceOp) + def orR: Bool = redop(OrReduceOp) - def andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, AndReduceOp) + def andR: Bool = redop(AndReduceOp) - def xorR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, XorReduceOp) + def xorR: Bool = redop(XorReduceOp) - override def <(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, LessOp, that) - override def >(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, GreaterOp, that) - override def <=(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, LessEqOp, that) - override def >=(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, GreaterEqOp, that) + override def <(that: UInt): Bool = + compop(LessOp, that) + override def >(that: UInt): Bool = + compop(GreaterOp, that) + override def <=(that: UInt): Bool = + compop(LessEqOp, that) + override def >=(that: UInt): Bool = + compop(GreaterEqOp, that) /** Dynamic not equals operator * @@ -537,11 +536,11 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @return a hardware [[Bool]] asserted if this $coll is equal to `that` * @group Comparison */ - def =/=(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, NotEqualOp, that) + def =/=(that: UInt): Bool = + compop(NotEqualOp, that) - def ===(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, EqualOp, that) + def ===(that: UInt): Bool = + compop(EqualOp, that) /** Unary not * @@ -554,27 +553,27 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U "Chisel 3.5" ) - def unary_!(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this === 0.U(1.W) + def unary_!(): Bool = this === 0.U(1.W) - override def <<(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, validateShiftAmount(that)) - override def <<(that: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + override def <<(that: Int): UInt = + binop(UInt(this.width + that), ShiftLeftOp, validateShiftAmount(that)) + override def <<(that: BigInt): UInt = this << castToInt(that, "Shift amount") - override def <<(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width.dynamicShiftLeft(that.width)), DynamicShiftLeftOp, that) - override def >>(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width.shiftRight(that)), ShiftRightOp, validateShiftAmount(that)) - override def >>(that: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + override def <<(that: UInt): UInt = + binop(UInt(this.width.dynamicShiftLeft(that.width)), DynamicShiftLeftOp, that) + override def >>(that: Int): UInt = + binop(UInt(this.width.shiftRight(that)), ShiftRightOp, validateShiftAmount(that)) + override def >>(that: BigInt): UInt = this >> castToInt(that, "Shift amount") - override def >>(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, UInt(this.width), DynamicShiftRightOp, that) + override def >>(that: UInt): UInt = + binop(UInt(this.width), DynamicShiftRightOp, that) /** * Circular shift to the left * @param that number of bits to rotate * @return UInt of same width rotated left n bits */ - def rotateLeft(n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = width match { + def rotateLeft(n: Int): UInt = width match { case _ if (n == 0) => this case KnownWidth(w) if (w <= 1) => this case KnownWidth(w) if n >= w => rotateLeft(n % w) @@ -587,7 +586,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @param that number of bits to rotate * @return UInt of same width rotated right n bits */ - def rotateRight(n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = width match { + def rotateRight(n: Int): UInt = width match { case _ if (n <= 0) => rotateLeft(-n) case KnownWidth(w) if (w <= 1) => this case KnownWidth(w) if n >= w => rotateRight(n % w) @@ -597,18 +596,15 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U private def dynamicShift( n: UInt, staticShift: (UInt, Int) => UInt - )( - using sourceInfo: SourceInfo, - compileOptions: CompileOptions ): UInt = n.asBools().zipWithIndex.foldLeft(this) { case (in, (en, sh)) => Mux(en, staticShift(in, 1 << sh), in) } - def rotateRight(n: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def rotateRight(n: UInt): UInt = dynamicShift(n, _ rotateRight _) - def rotateLeft(n: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + def rotateLeft(n: UInt): UInt = dynamicShift(n, _ rotateLeft _) /** Conditionally set or clear a bit @@ -618,10 +614,10 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @return a hrdware $coll with bit `off` set or cleared based on the value of `dat` * $unchangedWidth */ - def bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { - val bit = 1.U(1.W) << off - Mux(dat, this | bit, ~(~this | bit)) - } + // def bitSet(off: UInt, dat: Bool): UInt = { + // val bit = 1.U(1.W) << off + // Mux(dat, this | bit, ~(~(this()) | bit)) + // } // TODO: this eventually will be renamed as toSInt, once the existing toSInt // completes its deprecation phase. @@ -634,24 +630,21 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - def zext(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - pushOp(DefPrim(sourceInfo, SInt(width + 1), ConvertOp, ref)) + def zext: SInt = + pushOp(DefPrim(SInt(width + 1), ConvertOp, ref)) - override def asSInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - pushOp(DefPrim(sourceInfo, SInt(width), AsSIntOp, ref)) - override def asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = this + override def asSInt: SInt = + pushOp(DefPrim(SInt(width), AsSIntOp, ref)) + override def asUInt: UInt = this private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { this := that.asUInt } - private def subtractAsSInt(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt((this.width.max(that.width)) + 1), SubOp, that) + private def subtractAsSInt(that: UInt): SInt = + binop(SInt((this.width.max(that.width)) + 1), SubOp, that) } object UInt { @@ -712,23 +705,23 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S "Chisel 3.5" ) - def unary_-(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = 0.S - this + def unary_-(): SInt = 0.S - this - def unary_-%(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = 0.S -% this + def unary_-%(): SInt = 0.S -% this /** add (default - no growth) operator */ - override def +(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + override def +(that: SInt): SInt = this +% that /** subtract (default - no growth) operator */ - override def -(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + override def -(that: SInt): SInt = this -% that - override def *(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width + that.width), TimesOp, that) - override def /(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width + 1), DivideOp, that) - override def %(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width.min(that.width)), RemOp, that) + override def *(that: SInt): SInt = + binop(SInt(this.width + that.width), TimesOp, that) + override def /(that: SInt): SInt = + binop(SInt(this.width + 1), DivideOp, that) + override def %(that: SInt): SInt = + binop(SInt(this.width.min(that.width)), RemOp, that) /** Multiplication operator * @@ -738,9 +731,9 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S * $singleCycleMul * @group Arithmetic */ - def *(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = { + def *(that: UInt): SInt = { val thatToSInt = that.zext - val result = binop(sourceInfo, SInt(this.width + thatToSInt.width), TimesOp, thatToSInt) + val result = binop(SInt(this.width + thatToSInt.width), TimesOp, thatToSInt) result.tail(1).asSInt } @@ -772,16 +765,16 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S * $maxWidth * @group Arithmetic */ - def +&(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt((this.width.max(that.width)) + 1), AddOp, that) + def +&(that: SInt): SInt = + binop(SInt((this.width.max(that.width)) + 1), AddOp, that) - def +%(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + def +%(that: SInt): SInt = (this +& that).tail(1).asSInt - def -&(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt((this.width.max(that.width)) + 1), SubOp, that) + def -&(that: SInt): SInt = + binop(SInt((this.width.max(that.width)) + 1), SubOp, that) - def -%(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + def -%(that: SInt): SInt = (this -& that).tail(1).asSInt /** Bitwise and operator @@ -805,26 +798,26 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S * $maxWidth * @group Bitwise */ - def &(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, UInt(this.width.max(that.width)), BitAndOp, that).asSInt + def &(that: SInt): SInt = + binop(UInt(this.width.max(that.width)), BitAndOp, that).asSInt - def |(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, UInt(this.width.max(that.width)), BitOrOp, that).asSInt + def |(that: SInt): SInt = + binop(UInt(this.width.max(that.width)), BitOrOp, that).asSInt - def ^(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, UInt(this.width.max(that.width)), BitXorOp, that).asSInt + def ^(that: SInt): SInt = + binop(UInt(this.width.max(that.width)), BitXorOp, that).asSInt - def unary_~(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - unop(sourceInfo, UInt(width = width), BitNotOp).asSInt + def unary_~(): SInt = + unop(UInt(width = width), BitNotOp).asSInt - override def <(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, LessOp, that) - override def >(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, GreaterOp, that) - override def <=(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, LessEqOp, that) - override def >=(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, GreaterEqOp, that) + override def <(that: SInt): Bool = + compop(LessOp, that) + override def >(that: SInt): Bool = + compop(GreaterOp, that) + override def <=(that: SInt): Bool = + compop(LessEqOp, that) + override def >=(that: SInt): Bool = + compop(GreaterEqOp, that) /** Dynamic not equals operator * @@ -838,39 +831,36 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S * @return a hardware [[Bool]] asserted if this $coll is equal to `that` * @group Comparison */ - def =/=(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, NotEqualOp, that) + def =/=(that: SInt): Bool = + compop(NotEqualOp, that) - def ===(that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, EqualOp, that) + def ===(that: SInt): Bool = + compop(EqualOp, that) - def abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = { + def abs: SInt = { Mux(this < 0.S, -this, this) } - override def <<(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, validateShiftAmount(that)) - override def <<(that: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + override def <<(that: Int): SInt = + binop(SInt(this.width + that), ShiftLeftOp, validateShiftAmount(that)) + override def <<(that: BigInt): SInt = this << castToInt(that, "Shift amount") - override def <<(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width.dynamicShiftLeft(that.width)), DynamicShiftLeftOp, that) - override def >>(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width.shiftRight(that)), ShiftRightOp, validateShiftAmount(that)) - override def >>(that: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + override def <<(that: UInt): SInt = + binop(SInt(this.width.dynamicShiftLeft(that.width)), DynamicShiftLeftOp, that) + override def >>(that: Int): SInt = + binop(SInt(this.width.shiftRight(that)), ShiftRightOp, validateShiftAmount(that)) + override def >>(that: BigInt): SInt = this >> castToInt(that, "Shift amount") - override def >>(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = - binop(sourceInfo, SInt(this.width), DynamicShiftRightOp, that) + override def >>(that: UInt): SInt = + binop(SInt(this.width), DynamicShiftRightOp, that) - override def asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = pushOp( - DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref) + override def asUInt: UInt = pushOp( + DefPrim(UInt(this.width), AsUIntOp, ref) ) - override def asSInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = this + override def asSInt: SInt = this private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ) = { this := that.asSInt } @@ -898,7 +888,7 @@ sealed trait Reset extends Element with ToBoolable { "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - def asAsyncReset(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): AsyncReset + def asAsyncReset: AsyncReset } object Reset { @@ -923,26 +913,23 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Elem /** Not really supported */ def toPrintable: Printable = PString("Reset") - override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp( - DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref) + override def do_asUInt: UInt = pushOp( + DefPrim(UInt(this.width), AsUIntOp, ref) ) private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { this := that } - def asAsyncReset(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): AsyncReset = - pushOp(DefPrim(sourceInfo, AsyncReset(), AsAsyncResetOp, ref)) + def asAsyncReset: AsyncReset = + pushOp(DefPrim(AsyncReset(), AsAsyncResetOp, ref)) - def asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - pushOp(DefPrim(sourceInfo, Bool(), AsUIntOp, ref)) + def asBool: Bool = + pushOp(DefPrim(Bool(), AsUIntOp, ref)) - def toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = asBool + def toBool: Bool = asBool } object AsyncReset { @@ -968,26 +955,23 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends El /** Not really supported */ def toPrintable: Printable = PString("AsyncReset") - override def asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp( - DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref) + override def asUInt: UInt = pushOp( + DefPrim(UInt(this.width), AsUIntOp, ref) ) // TODO Is this right? private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { this := that.asBool.asAsyncReset } - def asAsyncReset(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): AsyncReset = this + def asAsyncReset: AsyncReset = this - def asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - pushOp(DefPrim(sourceInfo, Bool(), AsUIntOp, ref)) + def asBool: Bool = + pushOp(DefPrim(Bool(), AsUIntOp, ref)) - def toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = asBool + def toBool: Bool = asBool } // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth @@ -1044,17 +1028,17 @@ sealed class Bool() extends UInt(1.W) with Reset { * @group Bitwise */ - def &(that: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - binop(sourceInfo, Bool(), BitAndOp, that) + def &(that: Bool): Bool = + binop(Bool(), BitAndOp, that) - def |(that: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - binop(sourceInfo, Bool(), BitOrOp, that) + def |(that: Bool): Bool = + binop(Bool(), BitOrOp, that) - def ^(that: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - binop(sourceInfo, Bool(), BitXorOp, that) + def ^(that: Bool): Bool = + binop(Bool(), BitXorOp, that) - override def unary_~(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - unop(sourceInfo, Bool(), BitNotOp) + override def unary_~(): Bool = + unop(Bool(), BitNotOp) /** Logical or operator * @@ -1064,7 +1048,7 @@ sealed class Bool() extends UInt(1.W) with Reset { * @group Logical */ - def ||(that: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this | that + def ||(that: Bool): Bool = this | that /** Logical and operator * @@ -1073,19 +1057,19 @@ sealed class Bool() extends UInt(1.W) with Reset { * @note this is equivalent to [[Bool!.&(that:chisel3\.Bool)* Bool.&]] * @group Logical */ - def &&(that: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this & that + def &&(that: Bool): Bool = this & that /** Reinterprets this $coll as a clock */ @deprecated( "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - def asClock(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Clock = pushOp( - DefPrim(sourceInfo, Clock(), AsClockOp, ref) + def asClock: Clock = pushOp( + DefPrim(Clock(), AsClockOp, ref) ) - def asAsyncReset(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): AsyncReset = - pushOp(DefPrim(sourceInfo, AsyncReset(), AsAsyncResetOp, ref)) + def asAsyncReset: AsyncReset = + pushOp(DefPrim(AsyncReset(), AsAsyncResetOp, ref)) } object Bool { diff --git a/core/src/main/scala/chisel3/Clock.scala b/core/src/main/scala/chisel3/Clock.scala index aee6bc5a..d8a1f3ae 100644 --- a/core/src/main/scala/chisel3/Clock.scala +++ b/core/src/main/scala/chisel3/Clock.scala @@ -4,7 +4,6 @@ package chisel3 import chisel3.internal.Builder.pushOp import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo._ import chisel3.internal.firrtl.PrimOp.AsUIntOp object Clock { @@ -20,10 +19,10 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element private[chisel3] def typeEquivalent(that: Data): Boolean = this.getClass == that.getClass - override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = + override def connect(that: Data): Unit = that match { - case _: Clock | DontCare => super.connect(that)(sourceInfo, connectCompileOptions) - case _ => super.badConnect(that)(sourceInfo) + case _: Clock | DontCare => super.connect(that) + case _ => super.badConnect(that) } override def litOption: Option[BigInt] = None @@ -36,16 +35,13 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - def asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt.asBool + def asBool: Bool = this.asUInt.asBool - override def asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp( - DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref) + override def asUInt: UInt = pushOp( + DefPrim(UInt(this.width), AsUIntOp, ref) ) private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { this := that.asBool.asClock } diff --git a/core/src/main/scala/chisel3/CompileOptions.scala b/core/src/main/scala/chisel3/CompileOptions.scala index cdc05392..0261b21e 100644 --- a/core/src/main/scala/chisel3/CompileOptions.scala +++ b/core/src/main/scala/chisel3/CompileOptions.scala @@ -1,134 +1,134 @@ -// SPDX-License-Identifier: Apache-2.0 - -package chisel3 - -trait CompileOptions { - - /** Should Record connections require a strict match of fields. - * - * If true and the same fields aren't present in both source and sink, a MissingFieldException, - * MissingLeftFieldException, or MissingRightFieldException will be thrown. - */ - val connectFieldsMustMatch: Boolean - - /** When creating an object that takes a type argument, the argument must be unbound (a pure type). */ - val declaredTypeMustBeUnbound: Boolean - - /** If a connection operator fails, don't try the connection with the operands (source and sink) reversed. */ - val dontTryConnectionsSwapped: Boolean - - /** If connection directionality is not explicit, do not use heuristics to attempt to determine it. */ - val dontAssumeDirectionality: Boolean - - /** Check that referenced Data have actually been declared. */ - val checkSynthesizable: Boolean - - /** Require explicit assignment of DontCare to generate "x is invalid" */ - val explicitInvalidate: Boolean - - /** Should the reset type of Module be a Bool or a Reset */ - val inferModuleReset: Boolean - - /** If marked true, then any Module which consumes `inferModuleReset=false` must also mix in [[RequireSyncReset]] */ - def migrateInferModuleReset: Boolean = false - - /** Should connects emit as firrtl <= instead of <- */ - def emitStrictConnects: Boolean = true -} - -object CompileOptions { - -} - -object ExplicitCompileOptions { - - case class CompileOptionsClass( - // Should Record connections require a strict match of fields. - // If true and the same fields aren't present in both source and sink, a MissingFieldException, - // MissingLeftFieldException, or MissingRightFieldException will be thrown. - val connectFieldsMustMatch: Boolean, - // When creating an object that takes a type argument, the argument must be unbound (a pure type). - val declaredTypeMustBeUnbound: Boolean, - // If a connection operator fails, don't try the connection with the operands (source and sink) reversed. - val dontTryConnectionsSwapped: Boolean, - // If connection directionality is not explicit, do not use heuristics to attempt to determine it. - val dontAssumeDirectionality: Boolean, - // Check that referenced Data have actually been declared. - val checkSynthesizable: Boolean, - // Require an explicit DontCare assignment to generate a firrtl DefInvalid - val explicitInvalidate: Boolean, - // Should the reset type of Module be a Bool or a Reset - val inferModuleReset: Boolean) - extends CompileOptions - - // Collection of "not strict" connection compile options. - // These provide compatibility with existing code. - implicit val NotStrict: CompileOptionsClass = new CompileOptionsClass( - connectFieldsMustMatch = false, - declaredTypeMustBeUnbound = false, - dontTryConnectionsSwapped = false, - dontAssumeDirectionality = false, - checkSynthesizable = false, - explicitInvalidate = false, - inferModuleReset = false - ) { - override def migrateInferModuleReset = false - override def emitStrictConnects = false - override def copy( - connectFieldsMustMatch: Boolean = false, - declaredTypeMustBeUnbound: Boolean = false, - dontTryConnectionsSwapped: Boolean = false, - dontAssumeDirectionality: Boolean = false, - checkSynthesizable: Boolean = false, - explicitInvalidate: Boolean = false, - inferModuleReset: Boolean = false - ) = new CompileOptionsClass( - connectFieldsMustMatch, - declaredTypeMustBeUnbound, - dontTryConnectionsSwapped, - dontAssumeDirectionality, - checkSynthesizable, - explicitInvalidate, - inferModuleReset - ) { - override def migrateInferModuleReset = false - override def emitStrictConnects = false - } - } - - // Collection of "strict" connection compile options, preferred for new code. - implicit val Strict: CompileOptionsClass = new CompileOptionsClass( - connectFieldsMustMatch = true, - declaredTypeMustBeUnbound = true, - dontTryConnectionsSwapped = true, - dontAssumeDirectionality = true, - checkSynthesizable = true, - explicitInvalidate = true, - inferModuleReset = true - ) { - - override def migrateInferModuleReset = false - override def emitStrictConnects = true - - override def copy( - connectFieldsMustMatch: Boolean = true, - declaredTypeMustBeUnbound: Boolean = true, - dontTryConnectionsSwapped: Boolean = true, - dontAssumeDirectionality: Boolean = true, - checkSynthesizable: Boolean = true, - explicitInvalidate: Boolean = true, - inferModuleReset: Boolean = true - ) = new CompileOptionsClass( - connectFieldsMustMatch, - declaredTypeMustBeUnbound, - dontTryConnectionsSwapped, - dontAssumeDirectionality, - checkSynthesizable, - explicitInvalidate, - inferModuleReset - ) { - override def migrateInferModuleReset = false - override def emitStrictConnects = true - } - } -} +// // SPDX-License-Identifier: Apache-2.0 + +// package chisel3 + +// trait CompileOptions { + +// /** Should Record connections require a strict match of fields. +// * +// * If true and the same fields aren't present in both source and sink, a MissingFieldException, +// * MissingLeftFieldException, or MissingRightFieldException will be thrown. +// */ +// val connectFieldsMustMatch: Boolean + +// /** When creating an object that takes a type argument, the argument must be unbound (a pure type). */ +// val declaredTypeMustBeUnbound: Boolean + +// /** If a connection operator fails, don't try the connection with the operands (source and sink) reversed. */ +// val dontTryConnectionsSwapped: Boolean + +// /** If connection directionality is not explicit, do not use heuristics to attempt to determine it. */ +// val dontAssumeDirectionality: Boolean + +// /** Check that referenced Data have actually been declared. */ +// val checkSynthesizable: Boolean + +// /** Require explicit assignment of DontCare to generate "x is invalid" */ +// val explicitInvalidate: Boolean + +// /** Should the reset type of Module be a Bool or a Reset */ +// val inferModuleReset: Boolean + +// /** If marked true, then any Module which consumes `inferModuleReset=false` must also mix in [[RequireSyncReset]] */ +// def migrateInferModuleReset: Boolean = false + +// /** Should connects emit as firrtl <= instead of <- */ +// def emitStrictConnects: Boolean = true +// } + +// object CompileOptions { + +// } + +// object ExplicitCompileOptions { + +// case class CompileOptionsClass( +// // Should Record connections require a strict match of fields. +// // If true and the same fields aren't present in both source and sink, a MissingFieldException, +// // MissingLeftFieldException, or MissingRightFieldException will be thrown. +// val connectFieldsMustMatch: Boolean, +// // When creating an object that takes a type argument, the argument must be unbound (a pure type). +// val declaredTypeMustBeUnbound: Boolean, +// // If a connection operator fails, don't try the connection with the operands (source and sink) reversed. +// val dontTryConnectionsSwapped: Boolean, +// // If connection directionality is not explicit, do not use heuristics to attempt to determine it. +// val dontAssumeDirectionality: Boolean, +// // Check that referenced Data have actually been declared. +// val checkSynthesizable: Boolean, +// // Require an explicit DontCare assignment to generate a firrtl DefInvalid +// val explicitInvalidate: Boolean, +// // Should the reset type of Module be a Bool or a Reset +// val inferModuleReset: Boolean) +// extends CompileOptions + +// // Collection of "not strict" connection compile options. +// // These provide compatibility with existing code. +// implicit val NotStrict: CompileOptionsClass = new CompileOptionsClass( +// connectFieldsMustMatch = false, +// declaredTypeMustBeUnbound = false, +// dontTryConnectionsSwapped = false, +// dontAssumeDirectionality = false, +// checkSynthesizable = false, +// explicitInvalidate = false, +// inferModuleReset = false +// ) { +// override def migrateInferModuleReset = false +// override def emitStrictConnects = false +// override def copy( +// connectFieldsMustMatch: Boolean = false, +// declaredTypeMustBeUnbound: Boolean = false, +// dontTryConnectionsSwapped: Boolean = false, +// dontAssumeDirectionality: Boolean = false, +// checkSynthesizable: Boolean = false, +// explicitInvalidate: Boolean = false, +// inferModuleReset: Boolean = false +// ) = new CompileOptionsClass( +// connectFieldsMustMatch, +// declaredTypeMustBeUnbound, +// dontTryConnectionsSwapped, +// dontAssumeDirectionality, +// checkSynthesizable, +// explicitInvalidate, +// inferModuleReset +// ) { +// override def migrateInferModuleReset = false +// override def emitStrictConnects = false +// } +// } + +// // Collection of "strict" connection compile options, preferred for new code. +// implicit val Strict: CompileOptionsClass = new CompileOptionsClass( +// connectFieldsMustMatch = true, +// declaredTypeMustBeUnbound = true, +// dontTryConnectionsSwapped = true, +// dontAssumeDirectionality = true, +// checkSynthesizable = true, +// explicitInvalidate = true, +// inferModuleReset = true +// ) { + +// override def migrateInferModuleReset = false +// override def emitStrictConnects = true + +// override def copy( +// connectFieldsMustMatch: Boolean = true, +// declaredTypeMustBeUnbound: Boolean = true, +// dontTryConnectionsSwapped: Boolean = true, +// dontAssumeDirectionality: Boolean = true, +// checkSynthesizable: Boolean = true, +// explicitInvalidate: Boolean = true, +// inferModuleReset: Boolean = true +// ) = new CompileOptionsClass( +// connectFieldsMustMatch, +// declaredTypeMustBeUnbound, +// dontTryConnectionsSwapped, +// dontAssumeDirectionality, +// checkSynthesizable, +// explicitInvalidate, +// inferModuleReset +// ) { +// override def migrateInferModuleReset = false +// override def emitStrictConnects = true +// } +// } +// } diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index 5f9af175..6b514e21 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -6,7 +6,6 @@ import chisel3.experimental.{Analog, BaseModule, DataMirror} import chisel3.internal.Builder.pushCommand import chisel3.internal._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} import scala.collection.immutable.LazyList // Needed for 2.12 alias import scala.reflect.ClassTag @@ -54,12 +53,7 @@ object SpecifiedDirection { private[chisel3] def specifiedDirection[T <: Data]( source: T )(dir: SpecifiedDirection - )( - implicit compileOptions: CompileOptions ): T = { - if (compileOptions.checkSynthesizable) { - requireIsChiselType(source) - } val out = source.cloneType.asInstanceOf[T] out.specifiedDirection = dir out @@ -294,9 +288,6 @@ private[chisel3] object cloneSupertype { def apply[T <: Data]( elts: Seq[T], createdType: String - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { require(!elts.isEmpty, s"can't create $createdType with no inputs") @@ -417,18 +408,18 @@ object chiselTypeOf { * Thus, an error will be thrown if these are used on bound Data */ object Input { - def apply[T <: Data](source: T)(implicit compileOptions: CompileOptions): T = { + def apply[T <: Data](source: T): T = { SpecifiedDirection.specifiedDirection(source)(SpecifiedDirection.Input) } } object Output { - def apply[T <: Data](source: T)(implicit compileOptions: CompileOptions): T = { + def apply[T <: Data](source: T): T = { SpecifiedDirection.specifiedDirection(source)(SpecifiedDirection.Output) } } object Flipped { - def apply[T <: Data](source: T)(implicit compileOptions: CompileOptions): T = { + def apply[T <: Data](source: T): T = { SpecifiedDirection.specifiedDirection(source)(SpecifiedDirection.flip(source.specifiedDirection)) } } @@ -468,7 +459,7 @@ abstract class Data extends HasId with NamedComponent { if (_specifiedDirection != SpecifiedDirection.Unspecified) { this match { // Anything flies in compatibility mode - case t: Record if !t.compileOptions.dontAssumeDirectionality => + case t: Record => case _ => throw RebindingException(s"Attempted reassignment of user-specified direction to $this") } } @@ -586,64 +577,46 @@ abstract class Data extends HasId with NamedComponent { // TODO: refactor away this, this is outside the scope of Data private[chisel3] def allElements: Seq[Element] - private[chisel3] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = + private[chisel3] def badConnect(that: Data): Unit = throwException(s"cannot connect ${this} and ${that}") private[chisel3] def connect( that: Data - )( - implicit sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions ): Unit = { - if (connectCompileOptions.checkSynthesizable) { - requireIsHardware(this, "data to be connected") - requireIsHardware(that, "data to be connected") - this.topBinding match { - case _: ReadOnlyBinding => throwException(s"Cannot reassign to read-only $this") - case _ => // fine - } + requireIsHardware(this, "data to be connected") + requireIsHardware(that, "data to be connected") + this.topBinding match { + case _: ReadOnlyBinding => throwException(s"Cannot reassign to read-only $this") + case _ => // fine } - if (connectCompileOptions.emitStrictConnects) { - - try { - MonoConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.currentModule.get) - } catch { - case MonoConnectException(message) => - throwException( - s"Connection between sink ($this) and source ($that) failed @: $message" - ) - } - } else { - this.legacyConnect(that) + try { + MonoConnect.connect(this, that, Builder.currentModule.get) + } catch { + case MonoConnectException(message) => + throwException( + s"Connection between sink ($this) and source ($that) failed @: $message" + ) } } + private[chisel3] def bulkConnect( that: Data - )( - implicit sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions ): Unit = { - if (connectCompileOptions.checkSynthesizable) { - requireIsHardware(this, s"data to be bulk-connected") - requireIsHardware(that, s"data to be bulk-connected") + requireIsHardware(this, s"data to be bulk-connected") + requireIsHardware(that, s"data to be bulk-connected") (this.topBinding, that.topBinding) match { - case (_: ReadOnlyBinding, _: ReadOnlyBinding) => throwException(s"Both $this and $that are read-only") - // DontCare cannot be a sink (LHS) - case (_: DontCareBinding, _) => throw BiConnect.DontCareCantBeSink - case _ => // fine - } + case (_: ReadOnlyBinding, _: ReadOnlyBinding) => throwException(s"Both $this and $that are read-only") + // DontCare cannot be a sink (LHS) + case (_: DontCareBinding, _) => throw BiConnect.DontCareCantBeSink + case _ => // fine } - if (connectCompileOptions.emitStrictConnects) { - try { - BiConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.currentModule.get) - } catch { - case BiConnectException(message) => - throwException( - s"Connection between left ($this) and source ($that) failed @$message" - ) - } - } else { - this.legacyConnect(that) + try { + BiConnect.connect(this, that, Builder.currentModule.get) + } catch { + case BiConnectException(message) => + throwException( + s"Connection between left ($this) and source ($that) failed @$message" + ) } } @@ -683,8 +656,6 @@ abstract class Data extends HasId with NamedComponent { private[chisel3] final def ref: Arg = { def materializeWire(): Arg = { if (!Builder.currentModule.isDefined) throwException(s"internal error: cannot materialize ref for $this") - implicit val compileOptions = ExplicitCompileOptions.Strict - implicit val sourceInfo = UnlocatableSourceInfo WireDefault(this).ref } requireIsHardware(this) @@ -729,7 +700,7 @@ abstract class Data extends HasId with NamedComponent { } private[chisel3] def width: Width - private[chisel3] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit + private[chisel3] def legacyConnect(that: Data): Unit /** Internal API; Chisel users should look at chisel3.chiselTypeOf(...). * @@ -759,9 +730,9 @@ abstract class Data extends HasId with NamedComponent { * @param that the $coll to connect to * @group Connect */ - final def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = { + final def :=(that: => Data): Unit = { prefix(this) { - this.connect(that)(sourceInfo, connectionCompileOptions) + this.connect(that) } } @@ -772,9 +743,9 @@ abstract class Data extends HasId with NamedComponent { * @param that the $coll to connect to * @group Connect */ - final def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = { + final def <>(that: => Data): Unit = { prefix(this) { - this.bulkConnect(that)(sourceInfo, connectionCompileOptions) + this.bulkConnect(that) } } @@ -827,7 +798,7 @@ abstract class Data extends HasId with NamedComponent { * @note bit widths are NOT checked, may pad or drop bits from input * @note that should have known widths */ - def asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def asTypeOf[T <: Data](that: T): T = { val thatCloned = Wire(that.cloneTypeFull) thatCloned.connectFromBits(this.asUInt) thatCloned @@ -837,9 +808,6 @@ abstract class Data extends HasId with NamedComponent { */ private[chisel3] def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit /** Reinterpret cast to UInt. @@ -853,7 +821,7 @@ abstract class Data extends HasId with NamedComponent { "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - def asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt + def asUInt: UInt /** Default pretty printing */ def toPrintable: Printable @@ -874,7 +842,7 @@ object Data { * * @param lhs The [[Data]] hardware on the left-hand side of the equality */ - implicit class DataEquality[T <: Data](lhs: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { + implicit class DataEquality[T <: Data](lhs: T) { /** Dynamic recursive equality operator for generic [[Data]] * @@ -940,20 +908,13 @@ trait WireFactory { /** Construct a [[Wire]] from a type template * @param t The template from which to construct this wire */ - def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { - if (compileOptions.declaredTypeMustBeUnbound) { - requireIsChiselType(t, "wire type") - } + def apply[T <: Data](t: T): T = { val x = t.cloneTypeFull // Bind each element of x to being a Wire x.bind(WireBinding(Builder.forcedUserModule, Builder.currentWhen)) - pushCommand(DefWire(sourceInfo, x)) - if (!compileOptions.explicitInvalidate) { - pushCommand(DefInvalid(sourceInfo, x.ref)) - } - + pushCommand(DefWire(x)) x } } @@ -1043,9 +1004,6 @@ object WireDefault { private def applyImpl[T <: Data]( t: T, init: Data - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { val x = Wire(t) requireIsHardware(init, "wire initializer") @@ -1061,9 +1019,6 @@ object WireDefault { def apply[T <: Data]( t: T, init: DontCare.type - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { applyImpl(t, init) } @@ -1072,14 +1027,14 @@ object WireDefault { * @param t The type template used to construct this [[Wire]] * @param init The hardware value that will serve as the default value */ - def apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: Data](t: T, init: T): T = { applyImpl(t, init) } /** Construct a [[Wire]] with a default connection * @param init The hardware value that will serve as a type template and default value */ - def apply[T <: Data](init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: Data](init: T): T = { val model = (init match { // If init is a literal without forced width OR any non-literal, let width be inferred case init: Bits if !init.litIsForcedWidth.getOrElse(false) => init.cloneTypeWidth(Width()) @@ -1110,14 +1065,11 @@ final case object DontCare extends Element { private[chisel3] def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)") } - def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): UInt = { + def do_asUInt: UInt = { Builder.error("DontCare does not have a UInt representation") 0.U } diff --git a/core/src/main/scala/chisel3/Element.scala b/core/src/main/scala/chisel3/Element.scala index 39b7689c..22b6663f 100644 --- a/core/src/main/scala/chisel3/Element.scala +++ b/core/src/main/scala/chisel3/Element.scala @@ -4,7 +4,6 @@ package chisel3 import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal._ /** Element is a leaf data type: it cannot contain other [[Data]] objects. Example uses are for representing primitive @@ -56,14 +55,4 @@ abstract class Element extends Data { override def litOption: Option[BigInt] = litArgOption.map(_.num) private[chisel3] def litIsForcedWidth: Option[Boolean] = litArgOption.map(_.forcedWidth) - - private[chisel3] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = { - // If the source is a DontCare, generate a DefInvalid for the sink, - // otherwise, issue a Connect. - if (that == DontCare) { - pushCommand(DefInvalid(sourceInfo, Node(this))) - } else { - pushCommand(Connect(sourceInfo, Node(this), that.ref)) - } - } } diff --git a/core/src/main/scala/chisel3/IO.scala b/core/src/main/scala/chisel3/IO.scala index 1a28db1e..0e798f69 100644 --- a/core/src/main/scala/chisel3/IO.scala +++ b/core/src/main/scala/chisel3/IO.scala @@ -2,7 +2,6 @@ package chisel3 import chisel3.internal.requireIsChiselType // Fix ambiguous import import chisel3.internal.Builder -import chisel3.internal.sourceinfo.SourceInfo object IO { diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala index 41ae5879..0d77aa92 100644 --- a/core/src/main/scala/chisel3/Mem.scala +++ b/core/src/main/scala/chisel3/Mem.scala @@ -7,7 +7,6 @@ import firrtl.{ir => fir} import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo} object Mem { @@ -25,52 +24,34 @@ object Mem { def apply[T <: Data]( size: BigInt, t: T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Mem[T] = { - if (compileOptions.declaredTypeMustBeUnbound) { - requireIsChiselType(t, "memory type") - } + requireIsChiselType(t, "memory type") val mt = t.cloneTypeFull val mem = new Mem(mt, size) mt.bind(MemTypeBinding(mem)) - pushCommand(DefMemory(sourceInfo, mem, mt, size)) + pushCommand(DefMemory(mem, mt, size)) mem } - def apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Mem[T] = - apply(BigInt(size), t)(sourceInfo, compileOptions) + def apply[T <: Data](size: Int, t: T): Mem[T] = + apply(BigInt(size), t) } sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) extends HasId - with NamedComponent - with SourceInfoDoc { + with NamedComponent { _parent.foreach(_.addId(this)) // if the memory is created in a scope with an implicit clock (-> clockInst is defined), we will perform checks that // ensure memory ports are created with the same clock unless explicitly specified to use a different clock private val clockInst: Option[Clock] = Builder.currentClock - // Only kept for binary compatibility reasons, impossible for users to call - protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = clockWarning(sourceInfo, MemPortDirection.INFER) - - protected def clockWarning(sourceInfo: Option[SourceInfo], dir: MemPortDirection): Unit = { - // Turn into pretty String if possible, if not, Builder.deprecated will find one via stack trace - val infoStr = sourceInfo.collect { case SourceLine(file, line, col) => s"$file:$line:$col" } - Builder.deprecated( - "The clock used to initialize the memory is different than the one used to initialize the port. " + - "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0", - infoStr - ) - } // REVIEW TODO: make accessors (static/dynamic, read/write) combinations consistent. /** Creates a read accessor into the memory with static addressing. See the * class documentation of the memory for more detailed information. */ - def apply(idx: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply(idx: BigInt): T = { require(idx >= 0 && idx < length) apply(idx.asUInt, Builder.forcedClock) } @@ -78,45 +59,39 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) /** Creates a read accessor into the memory with static addressing. See the * class documentation of the memory for more detailed information. */ - def apply(idx: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - apply(BigInt(idx))(sourceInfo, compileOptions) + def apply(idx: Int): T = + apply(BigInt(idx)) /** Creates a read/write accessor into the memory with dynamic addressing. * See the class documentation of the memory for more detailed information. */ - def apply(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - apply_impl(idx, Builder.forcedClock, MemPortDirection.INFER, true) + def apply(idx: UInt): T = + do_apply_impl(idx, Builder.forcedClock, MemPortDirection.INFER, true) - def apply(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - apply_impl(idx, clock, MemPortDirection.INFER, false) + def apply(idx: UInt, clock: Clock): T = + do_apply_impl(idx, clock, MemPortDirection.INFER, false) /** Creates a read accessor into the memory with dynamic addressing. See the * class documentation of the memory for more detailed information. */ - def read(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - apply_impl(idx, Builder.forcedClock, MemPortDirection.READ, true) + def read(idx: UInt): T = + do_apply_impl(idx, Builder.forcedClock, MemPortDirection.READ, true) /** Creates a read accessor into the memory with dynamic addressing. * Takes a clock parameter to bind a clock that may be different * from the implicit clock. See the class documentation of the memory * for more detailed information. */ - def read(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - apply_impl(idx, clock, MemPortDirection.READ, false) + def read(idx: UInt, clock: Clock): T = + do_apply_impl(idx, clock, MemPortDirection.READ, false) - protected def apply_impl( + protected def do_apply_impl( idx: UInt, clock: Clock, dir: MemPortDirection, warn: Boolean - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { - if (warn && clockInst.isDefined && clock != clockInst.get) { - clockWarning(Some(sourceInfo), dir) - } - makePort(sourceInfo, idx, dir, clock) + makePort(idx, dir, clock) } /** Creates a write accessor into the memory. @@ -124,7 +99,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) * @param idx memory element index to write into * @param data new data to write */ - def write(idx: UInt, data: T)(implicit compileOptions: CompileOptions): Unit = + def write(idx: UInt, data: T): Unit = write_impl(idx, data, Builder.forcedClock, true) /** Creates a write accessor into the memory with a clock @@ -134,7 +109,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) * @param data new data to write * @param clock clock to bind to this accessor */ - def write(idx: UInt, data: T, clock: Clock)(implicit compileOptions: CompileOptions): Unit = + def write(idx: UInt, data: T, clock: Clock): Unit = write_impl(idx, data, clock, false) private def write_impl( @@ -142,14 +117,8 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) data: T, clock: Clock, warn: Boolean - )( - implicit compileOptions: CompileOptions ): Unit = { - if (warn && clockInst.isDefined && clock != clockInst.get) { - clockWarning(None, MemPortDirection.WRITE) - } - implicit val sourceInfo = UnlocatableSourceInfo - makePort(UnlocatableSourceInfo, idx, MemPortDirection.WRITE, clock) := data + makePort(idx, MemPortDirection.WRITE, clock) := data } /** Creates a masked write accessor into the memory. @@ -166,13 +135,12 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) data: T, mask: Seq[Bool] )( - implicit evidence: T <:< Vec[_], - compileOptions: CompileOptions + implicit evidence: T <:< Vec[_] ): Unit = masked_write_impl(idx, data, mask, Builder.forcedClock, true) /** Creates a masked write accessor into the memory with a clock - * that may be different from the implicit clock. + * that may be different from the implicitg clock. * * @param idx memory element index to write into * @param data new data to write @@ -188,8 +156,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) mask: Seq[Bool], clock: Clock )( - implicit evidence: T <:< Vec[_], - compileOptions: CompileOptions + implicit evidence: T <:< Vec[_] ): Unit = masked_write_impl(idx, data, mask, clock, false) @@ -201,13 +168,8 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) warn: Boolean )( implicit evidence: T <:< Vec[_], - compileOptions: CompileOptions ): Unit = { - implicit val sourceInfo = UnlocatableSourceInfo - if (warn && clockInst.isDefined && clock != clockInst.get) { - clockWarning(None, MemPortDirection.WRITE) - } - val accessor = makePort(sourceInfo, idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]] + val accessor = makePort(idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]] val dataVec = data.asInstanceOf[Vec[Data]] if (accessor.length != dataVec.length) { Builder.error(s"Mem write data must contain ${accessor.length} elements (found ${dataVec.length})") @@ -220,12 +182,9 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) } private def makePort( - sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection, clock: Clock - )( - using compileOptions: CompileOptions ): T = { if (Builder.currentModule != _parent) { throwException( @@ -233,10 +192,10 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) ) } requireIsHardware(idx, "memory port index") - val i = Vec.truncateIndex(idx, length)(compileOptions) + val i = Vec.truncateIndex(idx, length) val port = pushCommand( - DefMemPort(sourceInfo, t.cloneTypeFull, Node(this), dir, i.ref, clock.ref) + DefMemPort(t.cloneTypeFull, Node(this), dir, i.ref, clock.ref) ).id // Bind each element of port to being a MemoryPort port.bind(MemoryPortBinding(Builder.forcedUserModule, Builder.currentWhen)) @@ -253,13 +212,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) * @note when multiple conflicting writes are performed on a Mem element, the * result is undefined (unlike Vec, where the last assignment wins) */ -sealed class Mem[T <: Data] private[chisel3] (t: T, length: BigInt) extends MemBase(t, length) { - override protected def clockWarning(sourceInfo: Option[SourceInfo], dir: MemPortDirection): Unit = { - // Do not issue clock warnings on reads, since they are not clocked - if (dir != MemPortDirection.READ) - super.clockWarning(sourceInfo, dir) - } -} +sealed class Mem[T <: Data] private[chisel3] (t: T, length: BigInt) extends MemBase(t, length) object SyncReadMem { @@ -283,17 +236,12 @@ object SyncReadMem { size: BigInt, t: T, ruw: ReadUnderWrite = Undefined - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): SyncReadMem[T] = { - if (compileOptions.declaredTypeMustBeUnbound) { - requireIsChiselType(t, "memory type") - } + requireIsChiselType(t, "memory type") val mt = t.cloneTypeFull val mem = new SyncReadMem(mt, size, ruw) mt.bind(MemTypeBinding(mem)) - pushCommand(DefSeqMemory(sourceInfo, mem, mt, size, ruw)) + pushCommand(DefSeqMemory(mem, mt, size, ruw)) mem } @@ -301,22 +249,16 @@ object SyncReadMem { def apply[T <: Data]( size: Int, t: T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): SyncReadMem[T] = - apply(BigInt(size), t)(sourceInfo, compileOptions) + apply(BigInt(size), t) // Alternate signatures can't use default parameter values def apply[T <: Data]( size: Int, t: T, ruw: ReadUnderWrite - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): SyncReadMem[T] = - apply(BigInt(size), t, ruw)(sourceInfo, compileOptions) + apply(BigInt(size), t, ruw) } /** A sequential/synchronous-read, sequential/synchronous-write memory. @@ -332,13 +274,13 @@ object SyncReadMem { sealed class SyncReadMem[T <: Data] private[chisel3] (t: T, n: BigInt, val readUnderWrite: SyncReadMem.ReadUnderWrite) extends MemBase[T](t, n) { - override def read(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = + override def read(idx: UInt): T = read(idx = idx, en = true.B) - def read(idx: UInt, en: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = + def read(idx: UInt, en: Bool): T = _read_impl(idx, en, Builder.forcedClock, true) - def read(idx: UInt, en: Bool, clock: Clock)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = + def read(idx: UInt, en: Bool, clock: Clock): T = _read_impl(idx, en, clock, false) private def _read_impl( @@ -346,16 +288,13 @@ sealed class SyncReadMem[T <: Data] private[chisel3] (t: T, n: BigInt, val readU enable: Bool, clock: Clock, warn: Boolean - )( - using sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { val a = Wire(UInt(4.W)) a := DontCare var port: Option[T] = None when(enable) { a := addr - port = Some(super.apply(a, clock, MemPortDirection.READ, warn)) + port = Some(super.do_apply_impl(a, clock, MemPortDirection.READ, warn)) } port.get } diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 58e585ce..2c9e8189 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -8,7 +8,6 @@ import scala.collection.mutable.{ArrayBuffer, HashMap} import chisel3.internal._ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} import chisel3.experimental.BaseModule import _root_.firrtl.annotations.{IsModule, ModuleName, ModuleTarget} import _root_.firrtl.AnnotationSeq @@ -22,11 +21,10 @@ object Module { * * @return the input module `m` with Chisel metadata properly set */ - def apply[T <: BaseModule](bc: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: BaseModule](bc: => T): T = { if (Builder.readyForModuleConstr) { throwException( - "Error: Called Module() twice without instantiating a Module." + - sourceInfo.makeMessage(" See " + _) + "Error: Called Module() twice without instantiating a Module." ) } Builder.readyForModuleConstr = true @@ -54,8 +52,7 @@ object Module { if (Builder.readyForModuleConstr) { throwException( "Error: attempted to instantiate a Module, but nothing happened. " + - "This is probably due to rewrapping a Module instance with Module()." + - sourceInfo.makeMessage(" See " + _) + "This is probably due to rewrapping a Module instance with Module()." ) } Builder.currentModule = parent // Back to parent! @@ -75,8 +72,8 @@ object Module { // We use _component because Modules that don't generate them may still have one if (Builder.currentModule.isDefined && module._component.isDefined) { val component = module._component.get - pushCommand(DefInstance(sourceInfo, module, component.ports)) - module.initializeInParent(compileOptions) + pushCommand(DefInstance(module, component.ports)) + module.initializeInParent } module } @@ -92,9 +89,6 @@ object Module { private[chisel3] def do_pseudo_apply[T <: BaseModule]( bc: => T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { val parent = Builder.currentModule val module: T = bc // bc is actually evaluated here @@ -143,7 +137,7 @@ object Module { * * @note Module instantiations must be wrapped in a Module() call. */ -abstract class Module(implicit moduleCompileOptions: CompileOptions) extends RawModule { +abstract class Module extends RawModule { // Implicit clock and reset pins final val clock: Clock = IO(Input(Clock())).suggestName("clock") final val reset: Reset = IO(Input(mkReset)).suggestName("reset") @@ -168,16 +162,7 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw private[chisel3] def mkReset: Reset = { // Top module and compatibility mode use Bool for reset // Note that a Definition elaboration will lack a parent, but still not be a Top module - val inferReset = (_parent.isDefined) && moduleCompileOptions.inferModuleReset - if (moduleCompileOptions.migrateInferModuleReset && !moduleCompileOptions.inferModuleReset) { - this match { - case _: RequireSyncReset => // Good! It's been migrated. - case _ => // Bad! It hasn't been migrated. - Builder.error( - s"$desiredName is not inferring its module reset, but has not been marked `RequireSyncReset`. Please extend this trait." - ) - } - } + val inferReset = (_parent.isDefined) if (inferReset) Reset() else Bool() } @@ -186,10 +171,9 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw Builder.currentReset = Some(reset) Builder.clearPrefix() - private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { - implicit val sourceInfo = UnlocatableSourceInfo + private[chisel3] override def initializeInParent(): Unit = { - super.initializeInParent(parentCompileOptions) + super.initializeInParent clock := _override_clock.getOrElse(Builder.forcedClock) reset := _override_reset.getOrElse(Builder.forcedReset) } @@ -271,7 +255,7 @@ package experimental { /** Sets up this module in the parent context */ - private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit + private[chisel3] def initializeInParent: Unit // // Chisel Internals diff --git a/core/src/main/scala/chisel3/Mux.scala b/core/src/main/scala/chisel3/Mux.scala index a1f5a86d..3ec0d6ab 100644 --- a/core/src/main/scala/chisel3/Mux.scala +++ b/core/src/main/scala/chisel3/Mux.scala @@ -4,7 +4,6 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushOp -import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.firrtl._ import chisel3.internal.firrtl.PrimOp._ @@ -25,9 +24,6 @@ object Mux { cond: Bool, con: T, alt: T - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { requireIsHardware(cond, "mux condition") requireIsHardware(con, "mux true value") @@ -47,6 +43,6 @@ object Mux { dcWire.ref case _ => alt.ref } - pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, conRef, altRef)) + pushOp(DefPrim(d, MultiplexOp, cond.ref, conRef, altRef)) } } diff --git a/core/src/main/scala/chisel3/Num.scala b/core/src/main/scala/chisel3/Num.scala index 59f6db76..fc796352 100644 --- a/core/src/main/scala/chisel3/Num.scala +++ b/core/src/main/scala/chisel3/Num.scala @@ -4,8 +4,6 @@ package chisel3 import chisel3.internal.firrtl.{BinaryPoint, KnownBinaryPoint} -import chisel3.internal.sourceinfo.SourceInfo - // REVIEW TODO: Further discussion needed on what Num actually is. /** Abstract trait defining operations available on numeric-like hardware data types. @@ -40,7 +38,7 @@ trait Num[T <: Data] { * $maxWidth * @group Arithmetic */ - def +(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T + def +(that: T): T /** Multiplication operator * @@ -50,7 +48,7 @@ trait Num[T <: Data] { * $singleCycleMul * @group Arithmetic */ - def *(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T + def *(that: T): T /** Division operator * @@ -60,7 +58,7 @@ trait Num[T <: Data] { * @todo full rules * @group Arithmetic */ - def /(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T + def /(that: T): T /** Modulo operator * @@ -69,7 +67,7 @@ trait Num[T <: Data] { * $singleCycleDiv * @group Arithmetic */ - def %(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T + def %(that: T): T /** Subtraction operator * @@ -78,7 +76,7 @@ trait Num[T <: Data] { * $maxWidthPlusOne * @group Arithmetic */ - def -(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T + def -(that: T): T /** Less than operator * @@ -86,7 +84,7 @@ trait Num[T <: Data] { * @return a hardware [[Bool]] asserted if this $coll is less than `that` * @group Comparison */ - def <(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool + def <(that: T): Bool /** Less than or equal to operator * @@ -94,7 +92,7 @@ trait Num[T <: Data] { * @return a hardware [[Bool]] asserted if this $coll is less than or equal to `that` * @group Comparison */ - def <=(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool + def <=(that: T): Bool /** Greater than operator * @@ -102,7 +100,7 @@ trait Num[T <: Data] { * @return a hardware [[Bool]] asserted if this $coll is greater than `that` * @group Comparison */ - def >(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool + def >(that: T): Bool /** Greater than or equal to operator * @@ -110,7 +108,7 @@ trait Num[T <: Data] { * @return a hardware [[Bool]] asserted if this $coll is greather than or equal to `that` * @group Comparison */ - def >=(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool + def >=(that: T): Bool /** Absolute value operator * @@ -122,7 +120,7 @@ trait Num[T <: Data] { "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - def abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T + def abs: T /** Minimum operator * @@ -131,7 +129,7 @@ trait Num[T <: Data] { * $maxWidth * @group Arithmetic */ - def min(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = + def min(that: T): T = Mux(this < that, this.asInstanceOf[T], that) /** Maximum operator @@ -141,7 +139,7 @@ trait Num[T <: Data] { * $maxWidth * @group Arithmetic */ - def max(that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = + def max(that: T): T = Mux(this < that, that, this.asInstanceOf[T]) } diff --git a/core/src/main/scala/chisel3/Printf.scala b/core/src/main/scala/chisel3/Printf.scala index e7f942f4..1e98ba0f 100644 --- a/core/src/main/scala/chisel3/Printf.scala +++ b/core/src/main/scala/chisel3/Printf.scala @@ -4,7 +4,6 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushCommand -import chisel3.internal.sourceinfo.SourceInfo /** Prints a message in simulation * @@ -75,21 +74,6 @@ object printf { * @param data format string varargs containing data to print */ - // Private internal methods that serve to maintain binary - // compatibility after interpolator check updates - @deprecated("This Printf.apply method has been deprecated and will be removed in Chisel 3.6") - def apply(fmt: String, sourceInfo: SourceInfo, compileOptions: CompileOptions): Printf = - apply(fmt, Nil, sourceInfo, compileOptions) - - @deprecated("This Printf.apply method has been deprecated and will be removed in Chisel 3.6") - def apply( - fmt: String, - data: Seq[Bits], - sourceInfo: SourceInfo, - compileOptions: CompileOptions - ): Printf = - apply(Printable.pack(fmt, data: _*))(sourceInfo, compileOptions) - /** Prints a message in simulation * * Prints a message every cycle. If defined within the scope of a [[when]] block, the message @@ -104,17 +88,14 @@ object printf { * @see [[Printable]] documentation * @param pable [[Printable]] to print */ - def apply(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Printf = - printfWithReset(pable)(sourceInfo, compileOptions) + def apply(pable: Printable): Printf = + printfWithReset(pable) private[chisel3] def printfWithReset( pable: Printable - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Printf = { var printfId: Printf = null - when(!Module.reset.asBool) { + when(!(Module.reset.asBool)) { printfId = printfWithoutReset(pable) } printfId @@ -122,24 +103,18 @@ object printf { private[chisel3] def printfWithoutReset( pable: Printable - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Printf = { val clock = Builder.forcedClock val printfId = new Printf(pable) Printable.checkScope(pable) - pushCommand(chisel3.internal.firrtl.Printf(printfId, sourceInfo, clock.ref, pable)) + pushCommand(chisel3.internal.firrtl.Printf(printfId, clock.ref, pable)) printfId } private[chisel3] def printfWithoutReset( fmt: String, data: Bits* - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Printf = printfWithoutReset(Printable.pack(fmt, data: _*)) } diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 71bbcd00..01e5f9f5 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -8,7 +8,6 @@ import chisel3.experimental.BaseModule import chisel3.internal._ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.UnlocatableSourceInfo import _root_.firrtl.annotations.{IsModule, ModuleTarget} import scala.collection.immutable.VectorBuilder @@ -17,7 +16,7 @@ import scala.collection.immutable.VectorBuilder * multiple IO() declarations. */ @nowarn("msg=class Port") // delete when Port becomes private -abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends BaseModule { +abstract class RawModule extends BaseModule { // // RTL construction internals // @@ -35,8 +34,6 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends _component.get.asInstanceOf[DefModule].commands } - val compileOptions = moduleCompileOptions - // This could be factored into a common utility private def canBeNamed(id: HasId): Boolean = id match { case d: Data => @@ -117,7 +114,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends _component } - private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {} + private[chisel3] def initializeInParent: Unit = {} } trait RequireAsyncReset extends Module { diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala index bca679fa..7f73c27b 100644 --- a/core/src/main/scala/chisel3/Reg.scala +++ b/core/src/main/scala/chisel3/Reg.scala @@ -5,7 +5,6 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.SourceInfo /** Utility for constructing hardware registers * @@ -32,15 +31,13 @@ object Reg { * Value will not change unless the [[Reg]] is given a connection. * @param t The template from which to construct this wire */ - def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { - if (compileOptions.declaredTypeMustBeUnbound) { - requireIsChiselType(t, "reg type") - } + def apply[T <: Data](t: T): T = { + requireIsChiselType(t, "reg type") val reg = t.cloneTypeFull val clock = Node(Builder.forcedClock) reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen)) - pushCommand(DefReg(sourceInfo, reg, clock)) + pushCommand(DefReg(reg, clock)) reg } @@ -74,7 +71,7 @@ object Reg { object RegNext { /** Returns a register ''with an unset width'' connected to the signal `next` and with no reset value. */ - def apply[T <: Data](next: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: Data](next: T): T = { val model = (next match { case next: Bits => next.cloneTypeWidth(Width()) case next => next.cloneTypeFull @@ -88,7 +85,7 @@ object RegNext { } /** Returns a register ''with an unset width'' connected to the signal `next` and with the reset value `init`. */ - def apply[T <: Data](next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: Data](next: T, init: T): T = { val model = (next match { case next: Bits => next.cloneTypeWidth(Width()) case next => next.cloneTypeFull @@ -166,24 +163,22 @@ object RegInit { * @param t The type template used to construct this [[Reg]] * @param init The value the [[Reg]] is initialized to on reset */ - def apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { - if (compileOptions.declaredTypeMustBeUnbound) { - requireIsChiselType(t, "reg type") - } + def apply[T <: Data](t: T, init: T): T = { + requireIsChiselType(t, "reg type") val reg = t.cloneTypeFull val clock = Builder.forcedClock val reset = Builder.forcedReset reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen)) requireIsHardware(init, "reg initializer") - pushCommand(DefRegInit(sourceInfo, reg, clock.ref, reset.ref, init.ref)) + pushCommand(DefRegInit(reg, clock.ref, reset.ref, init.ref)) reg } /** Construct a [[Reg]] initialized on reset to the specified value. * @param init Initial value that serves as a type template and reset value */ - def apply[T <: Data](init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: Data](init: T): T = { val model = (init match { // If init is a literal without forced width OR any non-literal, let width be inferred case init: Bits if !init.litIsForcedWidth.getOrElse(false) => init.cloneTypeWidth(Width()) diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala index 0c2342cd..460954be 100644 --- a/core/src/main/scala/chisel3/SeqUtils.scala +++ b/core/src/main/scala/chisel3/SeqUtils.scala @@ -3,8 +3,6 @@ package chisel3 import chisel3.internal.{prefix, throwException} - -import chisel3.internal.sourceinfo._ import chisel3.internal.plugin.autoNameRecursively private[chisel3] object SeqUtils { @@ -16,7 +14,7 @@ private[chisel3] object SeqUtils { * Equivalent to r(n-1) ## ... ## r(1) ## r(0). * @note This returns a `0.U` if applied to a zero-element `Vec`. */ - def asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + def asUInt[T <: Bits](in: Seq[T]): UInt = { if (in.isEmpty) { 0.U } else if (in.tail.isEmpty) { @@ -34,7 +32,7 @@ private[chisel3] object SeqUtils { /** Outputs the number of elements that === true.B. */ - def count(in: Seq[Bool])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = in.size match { + def count(in: Seq[Bool]): UInt = in.size match { case 0 => 0.U case 1 => in.head case n => @@ -46,9 +44,6 @@ private[chisel3] object SeqUtils { */ def priorityMux[T <: Data]( in: Seq[(Bool, T)] - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { if (in.size == 1) { in.head._2 @@ -65,9 +60,6 @@ private[chisel3] object SeqUtils { */ def oneHotMux[T <: Data]( in: Iterable[(Bool, T)] - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): T = { if (in.tail.isEmpty) { in.head._2 diff --git a/core/src/main/scala/chisel3/When.scala b/core/src/main/scala/chisel3/When.scala index a4e5b195..940ebd8f 100644 --- a/core/src/main/scala/chisel3/When.scala +++ b/core/src/main/scala/chisel3/When.scala @@ -5,7 +5,6 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} object when { @@ -30,11 +29,8 @@ object when { def apply( cond: => Bool )(block: => Any - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): WhenContext = { - new WhenContext(sourceInfo, Some(() => cond), block, 0, Nil) + new WhenContext(Some(() => cond), block, 0, Nil) } /** Returns the current `when` condition @@ -52,8 +48,6 @@ object when { * }}} */ def cond: Bool = { - implicit val compileOptions = ExplicitCompileOptions.Strict - implicit val sourceInfo = UnlocatableSourceInfo val whens = Builder.whenStack whens.foldRight(true.B) { case (ctx, acc) => acc && ctx.localCond @@ -72,7 +66,6 @@ object when { * added by preprocessing the command queue. */ final class WhenContext private[chisel3] ( - sourceInfo: SourceInfo, cond: Option[() => Bool], block: => Any, firrtlDepth: Int, @@ -80,17 +73,15 @@ final class WhenContext private[chisel3] ( altConds: List[() => Bool]) { @deprecated("Use when(...) { ... }, this should never have been public", "Chisel 3.4.2") - def this(sourceInfo: SourceInfo, cond: Option[() => Bool], block: => Any, firrtlDepth: Int = 0) = - this(sourceInfo, cond, block, firrtlDepth, Nil) + def this(cond: Option[() => Bool], block: => Any, firrtlDepth: Int = 0) = + this(cond, block, firrtlDepth, Nil) private var scopeOpen = false /** Returns the local condition, inverted for an otherwise */ private[chisel3] def localCond: Bool = { - implicit val compileOptions = ExplicitCompileOptions.Strict - implicit val sourceInfo = UnlocatableSourceInfo val alt = altConds.foldRight(true.B) { - case (c, acc) => acc & !c() + case (c, acc) => acc & !(c()) } cond .map(alt && _()) @@ -106,11 +97,8 @@ final class WhenContext private[chisel3] ( def elsewhen( elseCond: => Bool )(block: => Any - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): WhenContext = { - new WhenContext(sourceInfo, Some(() => elseCond), block, firrtlDepth + 1, cond ++: altConds) + new WhenContext(Some(() => elseCond), block, firrtlDepth + 1, cond ++: altConds) } /** This block of logic gets executed only if the above conditions @@ -120,8 +108,8 @@ final class WhenContext private[chisel3] ( * assignment of the Bool node of the predicate in the correct * place. */ - def otherwise(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = - new WhenContext(sourceInfo, None, block, firrtlDepth + 1, cond ++: altConds) + def otherwise(block: => Any): Unit = + new WhenContext(None, block, firrtlDepth + 1, cond ++: altConds) def active: Boolean = scopeOpen @@ -134,8 +122,8 @@ final class WhenContext private[chisel3] ( /* * */ - if (firrtlDepth > 0) { pushCommand(AltBegin(sourceInfo)) } - cond.foreach(c => pushCommand(WhenBegin(sourceInfo, c().ref))) + if (firrtlDepth > 0) { pushCommand(AltBegin()) } + cond.foreach(c => pushCommand(WhenBegin(c().ref))) Builder.pushWhen(this) try { scopeOpen = true @@ -149,6 +137,6 @@ final class WhenContext private[chisel3] ( } scopeOpen = false Builder.popWhen() - cond.foreach(_ => pushCommand(WhenEnd(sourceInfo, firrtlDepth))) - if (cond.isEmpty) { pushCommand(OtherwiseEnd(sourceInfo, firrtlDepth)) } + cond.foreach(_ => pushCommand(WhenEnd(firrtlDepth))) + if (cond.isEmpty) { pushCommand(OtherwiseEnd(firrtlDepth)) } } diff --git a/core/src/main/scala/chisel3/dontTouch.scala b/core/src/main/scala/chisel3/dontTouch.scala index dc998ff5..f9f015f2 100644 --- a/core/src/main/scala/chisel3/dontTouch.scala +++ b/core/src/main/scala/chisel3/dontTouch.scala @@ -33,10 +33,8 @@ object dontTouch { * @param data The signal to be marked * @return Unmodified signal `data` */ - def apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T = { - if (compileOptions.checkSynthesizable) { - requireIsHardware(data, "Data marked dontTouch") - } + def apply[T <: Data](data: T): T = { + requireIsHardware(data, "Data marked dontTouch") annotate(new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(data.toNamed) }) data } diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala index 7bb0ac5d..c932228f 100644 --- a/core/src/main/scala/chisel3/experimental/Analog.scala +++ b/core/src/main/scala/chisel3/experimental/Analog.scala @@ -3,12 +3,10 @@ package chisel3.experimental import chisel3.internal.firrtl.Width -import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal._ import chisel3.{ ActualDirection, Bits, - CompileOptions, Data, Element, PString, @@ -49,7 +47,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element { // Used to enforce single bulk connect of Analog types, multi-attach is still okay // Note that this really means 1 bulk connect per Module because a port can // be connected in the parent module as well - private[chisel3] val biConnectLocs = mutable.Map.empty[BaseModule, SourceInfo] + // private[chisel3] val biConnectLocs = mutable.Map.empty[BaseModule] // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) @@ -75,14 +73,11 @@ final class Analog private (private[chisel3] val width: Width) extends Element { binding = target } - override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = + override def do_asUInt: UInt = throwException("Analog does not support asUInt") private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { throwException("Analog does not support connectFromBits") } diff --git a/core/src/main/scala/chisel3/experimental/Attach.scala b/core/src/main/scala/chisel3/experimental/Attach.scala index 1d32e941..a0c6121d 100644 --- a/core/src/main/scala/chisel3/experimental/Attach.scala +++ b/core/src/main/scala/chisel3/experimental/Attach.scala @@ -6,7 +6,6 @@ import chisel3.RawModule import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.SourceInfo object attach { // Exceptions that can be generated by attach @@ -15,12 +14,12 @@ object attach { AttachException(": Conditional attach is not allowed!") // Actual implementation - private[chisel3] def impl(elts: Seq[Analog], contextModule: BaseModule)(implicit sourceInfo: SourceInfo): Unit = { + private[chisel3] def impl(elts: Seq[Analog], contextModule: BaseModule): Unit = { if (Builder.whenDepth != 0) throw ConditionalAttachException // TODO Check that references are valid and can be attached - pushCommand(Attach(sourceInfo, elts.map(_.lref))) + pushCommand(Attach(elts.map(_.lref))) } /** Create an electrical connection between [[Analog]] components @@ -34,7 +33,7 @@ object attach { * attach(a1, a2) * }}} */ - def apply(elts: Analog*)(implicit sourceInfo: SourceInfo): Unit = { + def apply(elts: Analog*): Unit = { try { impl(elts, Builder.forcedUserModule) } catch { diff --git a/core/src/main/scala/chisel3/experimental/ChiselEnum.scala b/core/src/main/scala/chisel3/experimental/ChiselEnum.scala index b8317a02..d8c3fe0b 100644 --- a/core/src/main/scala/chisel3/experimental/ChiselEnum.scala +++ b/core/src/main/scala/chisel3/experimental/ChiselEnum.scala @@ -7,7 +7,6 @@ import chisel3._ import chisel3.internal.Builder.pushOp import chisel3.internal.firrtl.PrimOp._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo._ import chisel3.internal.{throwException, Binding, Builder, ChildBinding, ConstrainedBinding, InstanceId} import firrtl.annotations._ @@ -89,7 +88,7 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating override def cloneType: this.type = factory().asInstanceOf[this.type] - private[chisel3] def compop(sourceInfo: SourceInfo, op: PrimOp, other: EnumType): Bool = { + private[chisel3] def compop(op: PrimOp, other: EnumType): Bool = { requireIsHardware(this, "bits operated on") requireIsHardware(other, "bits operated on") @@ -97,7 +96,7 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating throwException(s"Enum types are not equivalent: ${this.enumTypeName}, ${other.enumTypeName}") } - pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref)) + pushOp(DefPrim(Bool(), op, this.ref, other.ref)) } private[chisel3] override def typeEquivalent(that: Data): Boolean = { @@ -107,32 +106,29 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating private[chisel3] override def connectFromBits( that: Bits - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Unit = { this := factory.apply(that.asUInt) } - def ===(that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, EqualOp, that) - def =/=(that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, NotEqualOp, that) - def <(that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, LessOp, that) - def >(that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, GreaterOp, that) - def <=(that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, LessEqOp, that) - def >=(that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - compop(sourceInfo, GreaterEqOp, that) - - override def asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - pushOp(DefPrim(sourceInfo, UInt(width), AsUIntOp, ref)) + def ===(that: EnumType): Bool = + compop(EqualOp, that) + def =/=(that: EnumType): Bool = + compop(NotEqualOp, that) + def <(that: EnumType): Bool = + compop(LessOp, that) + def >(that: EnumType): Bool = + compop(GreaterOp, that) + def <=(that: EnumType): Bool = + compop(LessEqOp, that) + def >=(that: EnumType): Bool = + compop(GreaterEqOp, that) + + override def asUInt: UInt = + pushOp(DefPrim(UInt(width), AsUIntOp, ref)) protected[chisel3] override def width: Width = factory.width - def isValid(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + def isValid: Bool = { if (litOption.isDefined) { true.B } else { @@ -145,7 +141,7 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating * @param s a [[scala.collection.Seq$ Seq]] of enumeration values to look for * @return a hardware [[Bool]] that indicates if this value matches any of the given values */ - final def isOneOf(s: Seq[EnumType])(using sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + final def isOneOf(s: Seq[EnumType]): Bool = { VecInit(s.map(this === _)).asUInt().orR() } @@ -158,12 +154,9 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating final def isOneOf( u1: EnumType, u2: EnumType* - )( - implicit sourceInfo: SourceInfo, - compileOptions: CompileOptions ): Bool = isOneOf(u1 +: u2.toSeq) - def next(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = { + def next: this.type = { if (litOption.isDefined) { val index = factory.all.indexOf(this) @@ -247,8 +240,6 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating protected def enumTypeName: String = factory.enumTypeName def toPrintable: Printable = { - implicit val sourceInfo = UnlocatableSourceInfo - implicit val compileOptions = ExplicitCompileOptions.Strict val allNames = factory.allNames.zip(factory.all) val nameSize = allNames.map(_._1.length).max def leftPad(str: String): String = { @@ -341,9 +332,6 @@ abstract class EnumFactory { private def castImpl( n: UInt, warn: Boolean - )( - implicit sourceInfo: SourceInfo, - connectionCompileOptions: CompileOptions ): Type = { if (n.litOption.isDefined) { enumInstances.find(_.litValue == n.litValue) match { @@ -374,7 +362,7 @@ abstract class EnumFactory { * @param n the UInt to cast * @return the equivalent Enum to the value of the cast UInt */ - def apply(n: UInt)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Type = + def apply(n: UInt): Type = castImpl(n, warn = true) /** Safely cast an [[UInt]] to the type of this Enum @@ -383,7 +371,7 @@ abstract class EnumFactory { * @return the equivalent Enum to the value of the cast UInt and a Bool indicating if the * Enum is valid */ - def safe(n: UInt)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): (Type, Bool) = { + def safe(n: UInt): (Type, Bool) = { val t = castImpl(n, warn = false) (t, t.isValid) } diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala index f4575ceb..4862e209 100644 --- a/core/src/main/scala/chisel3/experimental/package.scala +++ b/core/src/main/scala/chisel3/experimental/package.scala @@ -2,9 +2,7 @@ package chisel3 -import chisel3.ExplicitCompileOptions.Strict import chisel3.experimental.DataMirror.internal.chiselTypeClone -import chisel3.internal.sourceinfo.SourceInfo /** Package for experimental features, which may have their API changed, be removed, etc. * @@ -124,7 +122,7 @@ package object experimental { object BundleLiterals { implicit class AddBundleLiteralConstructor[T <: Record](x: T) { - def Lit(elems: (T => (Data, Data))*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def Lit(elems: (T => (Data, Data))*): T = { x._makeLit(elems: _*) } } @@ -141,7 +139,7 @@ package object experimental { * @param elems tuples of an index and a literal value * @return */ - def Lit(elems: (Int, T)*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { + def Lit(elems: (Int, T)*): Vec[T] = { x._makeLit(elems: _*) } } @@ -151,7 +149,7 @@ package object experimental { /** This provides an literal construction method for cases using * object `Vec` as in `Vec.Lit(1.U, 2.U)` */ - def Lit[T <: Data](elems: T*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { + def Lit[T <: Data](elems: T*): Vec[T] = { require(elems.nonEmpty, s"Lit.Vec(...) must have at least one element") val indexElements: Seq[(Int, T)] = elems.zipWithIndex.map { case (element, index) => (index, element) } val widestElement: T = elems.maxBy(_.getWidth) @@ -198,7 +196,7 @@ package object experimental { * Users may not instantiate this class directly. Instead they should use the implicit conversion from `Tuple2` in * `chisel3.experimental.conversions` */ - final class HWTuple2[+A <: Data, +B <: Data] private[chisel3] (val _1: A, val _2: B) extends Bundle()(Strict) { + final class HWTuple2[+A <: Data, +B <: Data] private[chisel3] (val _1: A, val _2: B) extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple2(chiselTypeClone(_1), chiselTypeClone(_2)) @@ -213,7 +211,7 @@ package object experimental { val _1: A, val _2: B, val _3: C) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple3( @@ -233,7 +231,7 @@ package object experimental { val _2: B, val _3: C, val _4: D) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple4( @@ -255,7 +253,7 @@ package object experimental { val _3: C, val _4: D, val _5: E) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple5( @@ -279,7 +277,7 @@ package object experimental { val _4: D, val _5: E, val _6: F) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple6( @@ -313,7 +311,7 @@ package object experimental { val _5: E, val _6: F, val _7: G) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple7( @@ -350,7 +348,7 @@ package object experimental { val _6: F, val _7: G, val _8: H) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple8( @@ -390,7 +388,7 @@ package object experimental { val _7: G, val _8: H, val _9: I) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple9( @@ -433,7 +431,7 @@ package object experimental { val _8: H, val _9: I, val _10: J) - extends Bundle()(Strict) { + extends Bundle() { // Because this implementation exists in chisel3.core, it cannot compile with the plugin, so we implement the behavior manually override protected def _usingPlugin: Boolean = true override protected def _cloneTypeImpl: Bundle = new HWTuple10( diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala index 82835052..46a2c134 100644 --- a/core/src/main/scala/chisel3/internal/BiConnect.scala +++ b/core/src/main/scala/chisel3/internal/BiConnect.scala @@ -7,8 +7,6 @@ import chisel3.experimental.{attach, Analog, BaseModule} import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{Connect, Converter, DefInvalid} -import scala.language.experimental.macros -import chisel3.internal.sourceinfo._ import _root_.firrtl.passes.CheckTypes /** @@ -44,8 +42,8 @@ private[chisel3] object BiConnect { BiConnectException(s": Right Record missing field ($field).") def MismatchedException(left: String, right: String) = BiConnectException(s": Left ($left) and Right ($right) have different types.") - def AttachAlreadyBulkConnectedException(sourceInfo: SourceInfo) = - BiConnectException(sourceInfo.makeMessage(": Analog previously bulk connected at " + _)) + def AttachAlreadyBulkConnectedException = + BiConnectException("Analog previously bulk connected") def DontCareCantBeSink = BiConnectException(": DontCare cannot be a connection sink (LHS)") @@ -74,8 +72,6 @@ private[chisel3] object BiConnect { * - 4 is a special case of 2 turning into 3 for some subfields, when either side's subfield at `extends Bundle/Record` has `emitStrictConnects = false` */ def connect( - sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: BaseModule @@ -84,22 +80,22 @@ private[chisel3] object BiConnect { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => try { - markAnalogConnected(sourceInfo, left_a, context_mod) - markAnalogConnected(sourceInfo, right_a, context_mod) + markAnalogConnected(left_a, context_mod) + markAnalogConnected(right_a, context_mod) } catch { // convert attach exceptions to BiConnectExceptions case attach.AttachException(message) => throw BiConnectException(message) } - attach.impl(Seq(left_a, right_a), context_mod)(sourceInfo) + attach.impl(Seq(left_a, right_a), context_mod) case (left_a: Analog, DontCare) => try { - markAnalogConnected(sourceInfo, left_a, context_mod) + markAnalogConnected(left_a, context_mod) } catch { // convert attach exceptions to BiConnectExceptions case attach.AttachException(message) => throw BiConnectException(message) } - pushCommand(DefInvalid(sourceInfo, left_a.lref)) - case (DontCare, right_a: Analog) => connect(sourceInfo, connectCompileOptions, right, left, context_mod) + pushCommand(DefInvalid(left_a.lref)) + case (DontCare, right_a: Analog) => connect(right, left, context_mod) case (left_e: Element, right_e: Element) => { - elemConnect(sourceInfo, connectCompileOptions, left_e, right_e, context_mod) + elemConnect(left_e, right_e, context_mod) // TODO(twigg): Verify the element-level classes are connectable } // Handle Vec case @@ -110,8 +106,7 @@ private[chisel3] object BiConnect { for (idx <- 0 until left_v.length) { try { - implicit val compileOptions = connectCompileOptions - connect(sourceInfo, connectCompileOptions, left_v(idx), right_v(idx), context_mod) + connect(left_v(idx), right_v(idx), context_mod) } catch { case BiConnectException(message) => throw BiConnectException(s"($idx)$message") } @@ -121,8 +116,7 @@ private[chisel3] object BiConnect { case (left_v: Vec[Data @unchecked], DontCare) => { for (idx <- 0 until left_v.length) { try { - implicit val compileOptions = connectCompileOptions - connect(sourceInfo, connectCompileOptions, left_v(idx), right, context_mod) + connect(left_v(idx), right, context_mod) } catch { case BiConnectException(message) => throw BiConnectException(s"($idx)$message") } @@ -132,8 +126,7 @@ private[chisel3] object BiConnect { case (DontCare, right_v: Vec[Data @unchecked]) => { for (idx <- 0 until right_v.length) { try { - implicit val compileOptions = connectCompileOptions - connect(sourceInfo, connectCompileOptions, left, right_v(idx), context_mod) + connect(left, right_v(idx), context_mod) } catch { case BiConnectException(message) => throw BiConnectException(s"($idx)$message") } @@ -142,41 +135,32 @@ private[chisel3] object BiConnect { // Handle Records defined in Chisel._ code by emitting a FIRRTL bulk // connect when possible and a partial connect otherwise case pair @ (left_r: Record, right_r: Record) => - val emitStrictConnects: Boolean = - left_r.compileOptions.emitStrictConnects && right_r.compileOptions.emitStrictConnects + val emitStrictConnects: Boolean = true // chisel3 <> is commutative but FIRRTL <- is not val flipConnection = !MonoConnect.canBeSink(left_r, context_mod) || !MonoConnect.canBeSource(right_r, context_mod) val (newLeft, newRight) = if (flipConnection) (right_r, left_r) else (left_r, right_r) - recordConnect(sourceInfo, connectCompileOptions, left_r, right_r, context_mod) + recordConnect(left_r, right_r, context_mod) // Handle Records connected to DontCare case (left_r: Record, DontCare) => - if (!left_r.compileOptions.emitStrictConnects) { - left.legacyConnect(right)(sourceInfo) - } else { - // For each field in left, descend with right - for ((field, left_sub) <- left_r.elements) { - try { - connect(sourceInfo, connectCompileOptions, left_sub, right, context_mod) - } catch { - case BiConnectException(message) => throw BiConnectException(s".$field$message") - } + // For each field in left, descend with right + for ((field, left_sub) <- left_r.elements) { + try { + connect(left_sub, right, context_mod) + } catch { + case BiConnectException(message) => throw BiConnectException(s".$field$message") } } case (DontCare, right_r: Record) => - if (!right_r.compileOptions.emitStrictConnects) { - left.legacyConnect(right)(sourceInfo) - } else { - // For each field in left, descend with right - for ((field, right_sub) <- right_r.elements) { - try { - connect(sourceInfo, connectCompileOptions, left, right_sub, context_mod) - } catch { - case BiConnectException(message) => throw BiConnectException(s".$field$message") - } + // For each field in left, descend with right + for ((field, right_sub) <- right_r.elements) { + try { + connect(left, right_sub, context_mod) + } catch { + case BiConnectException(message) => throw BiConnectException(s".$field$message") } } @@ -187,8 +171,6 @@ private[chisel3] object BiConnect { // Do connection of two Records def recordConnect( - sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, left_r: Record, right_r: Record, context_mod: BaseModule @@ -197,23 +179,17 @@ private[chisel3] object BiConnect { // For each field in left, descend with right. // Don't bother doing this check if we don't expect it to necessarily pass. - if (connectCompileOptions.connectFieldsMustMatch) { - for ((field, right_sub) <- right_r.elements) { - if (!left_r.elements.isDefinedAt(field)) { - throw MissingLeftFieldException(field) - } + for ((field, right_sub) <- right_r.elements) { + if (!left_r.elements.isDefinedAt(field)) { + throw MissingLeftFieldException(field) } } // For each field in left, descend with right for ((field, left_sub) <- left_r.elements) { try { right_r.elements.get(field) match { - case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod) - case None => { - if (connectCompileOptions.connectFieldsMustMatch) { - throw MissingRightFieldException(field) - } - } + case Some(right_sub) => connect(left_sub, right_sub, context_mod) + case None => throw MissingRightFieldException(field) } } catch { case BiConnectException(message) => throw BiConnectException(s".$field$message") @@ -235,22 +211,18 @@ private[chisel3] object BiConnect { private[chisel3] def canBulkConnectAggregates( sink: Aggregate, source: Aggregate, - sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, context_mod: BaseModule ): Boolean = { // check that the aggregates have the same types def typeCheck = CheckTypes.validConnect( - Converter.extractType(sink, sourceInfo), - Converter.extractType(source, sourceInfo) + Converter.extractType(sink), + Converter.extractType(source) ) // check records live in appropriate contexts def contextCheck = MonoConnect.aggregateConnectContextCheck( - sourceInfo, - connectCompileOptions, sink, source, context_mod @@ -276,33 +248,31 @@ private[chisel3] object BiConnect { // These functions (finally) issue the connection operation // Issue with right as sink, left as source - private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = { + private def issueConnectL2R(left: Element, right: Element): Unit = { // Source and sink are ambiguous in the case of a Bi/Bulk Connect (<>). // If either is a DontCareBinding, just issue a DefInvalid for the other, // otherwise, issue a Connect. (left.topBinding, right.topBinding) match { - case (lb: DontCareBinding, _) => pushCommand(DefInvalid(sourceInfo, right.lref)) - case (_, rb: DontCareBinding) => pushCommand(DefInvalid(sourceInfo, left.lref)) - case (_, _) => pushCommand(Connect(sourceInfo, right.lref, left.ref)) + case (lb: DontCareBinding, _) => pushCommand(DefInvalid(right.lref)) + case (_, rb: DontCareBinding) => pushCommand(DefInvalid(left.lref)) + case (_, _) => pushCommand(Connect(right.lref, left.ref)) } } // Issue with left as sink, right as source - private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = { + private def issueConnectR2L(left: Element, right: Element): Unit = { // Source and sink are ambiguous in the case of a Bi/Bulk Connect (<>). // If either is a DontCareBinding, just issue a DefInvalid for the other, // otherwise, issue a Connect. (left.topBinding, right.topBinding) match { - case (lb: DontCareBinding, _) => pushCommand(DefInvalid(sourceInfo, right.lref)) - case (_, rb: DontCareBinding) => pushCommand(DefInvalid(sourceInfo, left.lref)) - case (_, _) => pushCommand(Connect(sourceInfo, left.lref, right.ref)) + case (lb: DontCareBinding, _) => pushCommand(DefInvalid(right.lref)) + case (_, rb: DontCareBinding) => pushCommand(DefInvalid(left.lref)) + case (_, _) => pushCommand(Connect(left.lref, right.ref)) } } // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. def elemConnect( - implicit sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, _left: Element, _right: Element, context_mod: BaseModule @@ -369,13 +339,7 @@ private[chisel3] object BiConnect { case (Input, Input) => throw BothDriversException case (Output, Output) => throw BothDriversException - case (Internal, Internal) => { - if (connectCompileOptions.dontAssumeDirectionality) { - throw UnknownDriverException - } else { - issueConnectR2L(left, right) - } - } + case (Internal, Internal) => throw UnknownDriverException } } @@ -391,18 +355,8 @@ private[chisel3] object BiConnect { case (Input, Input) => throw NeitherDriverException case (Output, Output) => throw BothDriversException - case (_, Internal) => - if (connectCompileOptions.dontAssumeDirectionality) { - throw UnknownRelationException - } else { - issueConnectR2L(left, right) - } - case (Internal, _) => - if (connectCompileOptions.dontAssumeDirectionality) { - throw UnknownRelationException - } else { - issueConnectR2L(left, right) - } + case (_, Internal) => throw UnknownRelationException + case (Internal, _) => throw UnknownRelationException } } @@ -412,12 +366,10 @@ private[chisel3] object BiConnect { } // This function checks if analog element-level attaching is allowed, then marks the Analog as connected - def markAnalogConnected(implicit sourceInfo: SourceInfo, analog: Analog, contextModule: BaseModule): Unit = { + def markAnalogConnected(analog: Analog, contextModule: BaseModule): Unit = { analog.biConnectLocs.get(contextModule) match { - case Some(sl) => throw AttachAlreadyBulkConnectedException(sl) + case Some(sl) => throw AttachAlreadyBulkConnectedException case None => // Do nothing } - // Mark bulk connected - analog.biConnectLocs(contextModule) = sourceInfo } } diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala index 1389d508..51db0fe7 100644 --- a/core/src/main/scala/chisel3/internal/MonoConnect.scala +++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala @@ -7,7 +7,6 @@ import chisel3.experimental.{Analog, BaseModule, UnsafeEnum} import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{Connect, Converter, DefInvalid} -import chisel3.internal.sourceinfo.SourceInfo import _root_.firrtl.passes.CheckTypes import scala.annotation.tailrec @@ -90,8 +89,6 @@ private[chisel3] object MonoConnect { * This gives the user a 'path' to where in the connections things went wrong. */ def connect( - sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, sink: Data, source: Data, context_mod: BaseModule @@ -100,35 +97,34 @@ private[chisel3] object MonoConnect { // Handle legal element cases, note (Bool, Bool) is caught by the first two, as Bool is a UInt case (sink_e: Bool, source_e: UInt) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: UInt, source_e: Bool) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: UInt, source_e: UInt) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: SInt, source_e: SInt) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: Clock, source_e: Clock) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: AsyncReset, source_e: AsyncReset) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: ResetType, source_e: Reset) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: Reset, source_e: ResetType) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: EnumType, source_e: UnsafeEnum) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: EnumType, source_e: EnumType) if sink_e.typeEquivalent(source_e) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) case (sink_e: UnsafeEnum, source_e: UInt) => - elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod) + elemConnect(sink_e, source_e, context_mod) // Handle Vec case case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) => if (sink_v.length != source_v.length) { throw MismatchedVecException } for (idx <- 0 until sink_v.length) { try { - implicit val compileOptions = connectCompileOptions - connect(sourceInfo, connectCompileOptions, sink_v(idx), source_v(idx), context_mod) + connect(sink_v(idx), source_v(idx), context_mod) } catch { case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message") } @@ -137,8 +133,7 @@ private[chisel3] object MonoConnect { case (sink_v: Vec[Data @unchecked], DontCare) => for (idx <- 0 until sink_v.length) { try { - implicit val compileOptions = connectCompileOptions - connect(sourceInfo, connectCompileOptions, sink_v(idx), source, context_mod) + connect(sink_v(idx), source, context_mod) } catch { case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message") } @@ -150,11 +145,9 @@ private[chisel3] object MonoConnect { for ((field, sink_sub) <- sink_r.elements) { try { source_r.elements.get(field) match { - case Some(source_sub) => connect(sourceInfo, connectCompileOptions, sink_sub, source_sub, context_mod) + case Some(source_sub) => connect(sink_sub, source_sub, context_mod) case None => { - if (connectCompileOptions.connectFieldsMustMatch) { - throw MissingFieldException(field) - } + throw MissingFieldException(field) } } } catch { @@ -166,7 +159,7 @@ private[chisel3] object MonoConnect { // For each field, descend with right for ((field, sink_sub) <- sink_r.elements) { try { - connect(sourceInfo, connectCompileOptions, sink_sub, source, context_mod) + connect(sink_sub, source, context_mod) } catch { case MonoConnectException(message) => throw MonoConnectException(s".$field$message") } @@ -174,7 +167,7 @@ private[chisel3] object MonoConnect { // Source is DontCare - it may be connected to anything. It generates a defInvalid for the sink. case (sink: Element, DontCare) => - pushCommand(DefInvalid(sourceInfo, sink.lref)) + pushCommand(DefInvalid(sink.lref)) // DontCare as a sink is illegal. case (DontCare, _) => throw DontCareCantBeSink // Analog is illegal in mono connections. @@ -193,8 +186,6 @@ private[chisel3] object MonoConnect { * @return whether the source and sink exist in an appropriate context to be connected */ private[chisel3] def aggregateConnectContextCheck( - implicit sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, sink: Aggregate, source: Aggregate, context_mod: BaseModule @@ -241,11 +232,10 @@ private[chisel3] object MonoConnect { case _ => false } // Thus, right node better be a port node and thus have a direction - if (!source_is_port) { !connectCompileOptions.dontAssumeDirectionality } + if (!source_is_port) { false } else if (sinkCanBeInput) { - if (source.direction == Output) { - !connectCompileOptions.dontTryConnectionsSwapped - } else { false } + if (source.direction == Output) { true } + else { false } } else { true } } @@ -266,7 +256,7 @@ private[chisel3] object MonoConnect { // Note: This includes case when sink and source in same module but in parent else if ((sink_parent == context_mod) && (source_parent == context_mod)) { // Thus both nodes must be ports and have a direction - if (!source_is_port) { !connectCompileOptions.dontAssumeDirectionality } + if (!source_is_port) { false } else if (sink_is_port) { // NOTE: Workaround for bulk connecting non-agnostified FIRRTL ports // See: https://github.com/freechipsproject/firrtl/issues/1703 @@ -323,13 +313,11 @@ private[chisel3] object MonoConnect { private[chisel3] def canBulkConnectAggregates( sink: Aggregate, source: Aggregate, - sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, context_mod: BaseModule ): Boolean = { // Assuming we're using a <>, check if a bulk connect is valid in that case def biConnectCheck = - BiConnect.canBulkConnectAggregates(sink, source, sourceInfo, connectCompileOptions, context_mod) + BiConnect.canBulkConnectAggregates(sink, source, context_mod) // Check that the Aggregate can be driven (not bidirectional or an input) to match Chisel semantics def sinkCanBeDrivenCheck: Boolean = @@ -339,20 +327,18 @@ private[chisel3] object MonoConnect { } // This function (finally) issues the connection operation - private def issueConnect(sink: Element, source: Element)(implicit sourceInfo: SourceInfo): Unit = { + private def issueConnect(sink: Element, source: Element): Unit = { // If the source is a DontCare, generate a DefInvalid for the sink, // otherwise, issue a Connect. source.topBinding match { - case b: DontCareBinding => pushCommand(DefInvalid(sourceInfo, sink.lref)) - case _ => pushCommand(Connect(sourceInfo, sink.lref, source.ref)) + case b: DontCareBinding => pushCommand(DefInvalid(sink.lref)) + case _ => pushCommand(Connect(sink.lref, source.ref)) } } // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. def elemConnect( - implicit sourceInfo: SourceInfo, - connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: BaseModule @@ -398,15 +384,9 @@ private[chisel3] object MonoConnect { case (Internal, Input) => issueConnect(sink, source) case (Output, Output) => issueConnect(sink, source) case (Output, Input) => issueConnect(sink, source) - case (_, Internal) => { - if (!(connectCompileOptions.dontAssumeDirectionality)) { - issueConnect(sink, source) - } else { - throw UnreadableSourceException(sink, source) - } - } - case (Input, Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) - case (Input, _) => throw UnwritableSinkException(sink, source) + case (_, Internal) => throw UnreadableSourceException(sink, source) + case (Input, Output) => issueConnect(source, sink) + case (Input, _) => throw UnwritableSinkException(sink, source) } } @@ -434,11 +414,7 @@ private[chisel3] object MonoConnect { case (Input, Output) => issueConnect(sink, source) case (Output, _) => throw UnwritableSinkException(sink, source) case (_, Internal) => { - if (!(connectCompileOptions.dontAssumeDirectionality)) { - issueConnect(sink, source) - } else { - throw UnreadableSourceException(sink, source) - } + issueConnect(sink, source) } case (Internal, _) => throw UnwritableSinkException(sink, source) } diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index 93676fef..3c4a01b2 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -3,7 +3,6 @@ package chisel3.internal.firrtl import chisel3._ import chisel3.experimental._ -import chisel3.internal.sourceinfo.{NoSourceInfo, SourceInfo, SourceLine, UnlocatableSourceInfo} import firrtl.{ir => fir} import chisel3.internal.{castToInt, throwException, HasId} @@ -32,22 +31,19 @@ private[chisel3] object Converter { throwException(fullMsg) } - def getRef(id: HasId, sourceInfo: SourceInfo): Arg = + def getRef(id: HasId): Arg = id.getOptionRef.getOrElse { val module = id._parent.map(m => s" '$id' was defined in module '$m'.").getOrElse("") - val loc = sourceInfo.makeMessage(" " + _) + val loc = "" reportInternalError(s"Could not get ref for '$id'$loc!$module") } - private def clonedModuleIOError(mod: BaseModule, name: String, sourceInfo: SourceInfo): Nothing = { - val loc = sourceInfo.makeMessage(" " + _) + private def clonedModuleIOError(mod: BaseModule, name: String): Nothing = { + val loc = "" reportInternalError(s"Trying to convert a cloned IO of $mod inside of $mod itself$loc!") } - def convert(info: SourceInfo): fir.Info = info match { - case _: NoSourceInfo => fir.NoInfo - case SourceLine(fn, line, col) => fir.FileInfo(fir.StringLit(s"$fn $line:$col")) - } + // def convert(info: SourceInfo): fir.Info = fir.NoInfo def convert(op: PrimOp): fir.PrimOp = firrtl.PrimOps.fromString(op.name) @@ -61,24 +57,24 @@ private[chisel3] object Converter { // TODO // * Memoize? // * Move into the Chisel IR? - def convert(arg: Arg, ctx: Component, info: SourceInfo): fir.Expression = arg match { + def convert(arg: Arg, ctx: Component): fir.Expression = arg match { case Node(id) => - convert(getRef(id, info), ctx, info) + convert(getRef(id), ctx) case Ref(name) => fir.Reference(name, fir.UnknownType) case Slot(imm, name) => - fir.SubField(convert(imm, ctx, info), name, fir.UnknownType) + fir.SubField(convert(imm, ctx), name, fir.UnknownType) case OpaqueSlot(imm) => - convert(imm, ctx, info) + convert(imm, ctx) case Index(imm, ILit(idx)) => - fir.SubIndex(convert(imm, ctx, info), castToInt(idx, "Index"), fir.UnknownType) + fir.SubIndex(convert(imm, ctx), castToInt(idx, "Index"), fir.UnknownType) case Index(imm, value) => - fir.SubAccess(convert(imm, ctx, info), convert(value, ctx, info), fir.UnknownType) + fir.SubAccess(convert(imm, ctx), convert(value, ctx), fir.UnknownType) case ModuleIO(mod, name) => if (mod eq ctx.id) fir.Reference(name, fir.UnknownType) - else fir.SubField(fir.Reference(getRef(mod, info).name, fir.UnknownType), name, fir.UnknownType) + else fir.SubField(fir.Reference(getRef(mod).name, fir.UnknownType), name, fir.UnknownType) case ModuleCloneIO(mod, name) => - if (mod eq ctx.id) clonedModuleIOError(mod, name, info) + if (mod eq ctx.id) clonedModuleIOError(mod, name) else fir.Reference(name) case u @ ULit(n, UnknownWidth()) => fir.UIntLiteral(n, fir.IntWidth(u.minWidth)) @@ -87,7 +83,7 @@ private[chisel3] object Converter { case slit @ SLit(n, w) => fir.SIntLiteral(n, convert(w)) val unsigned = if (n < 0) (BigInt(1) << slit.width.get) + n else n - val uint = convert(ULit(unsigned, slit.width), ctx, info) + val uint = convert(ULit(unsigned, slit.width), ctx) fir.DoPrim(firrtl.PrimOps.AsSInt, Seq(uint), Seq.empty, fir.UnknownType) // TODO Simplify case lit: ILit => @@ -100,7 +96,7 @@ private[chisel3] object Converter { val consts = e.args.collect { case ILit(i) => i } val args = e.args.flatMap { case _: ILit => None - case other => Some(convert(other, ctx, e.sourceInfo)) + case other => Some(convert(other, ctx, fir.NoInfo)) } val expr = e.op.name match { case "mux" => @@ -109,86 +105,87 @@ private[chisel3] object Converter { case _ => fir.DoPrim(convert(e.op), args, consts, fir.UnknownType) } - Some(fir.DefNode(convert(e.sourceInfo), e.name, expr)) - case e @ DefWire(info, id) => - Some(fir.DefWire(convert(info), e.name, extractType(id, info))) - case e @ DefReg(info, id, clock) => + Some(fir.DefNode(fir.NoInfo, e.name, expr)) + case e @ DefWire(id) => + Some(fir.DefWire(fir.NoInfo, e.name, extractType(id))) + case e @ DefReg(id, clock) => Some( fir.DefRegister( - convert(info), + fir.NoInfo, e.name, - extractType(id, info), - convert(clock, ctx, info), + extractType(id), + convert(clock, ctx), firrtl.Utils.zero, - convert(getRef(id, info), ctx, info) + convert(getRef(id), ctx) ) ) - case e @ DefRegInit(info, id, clock, reset, init) => + case e @ DefRegInit(id, clock, reset, init) => Some( fir.DefRegister( - convert(info), + fir.NoInfo, e.name, - extractType(id, info), - convert(clock, ctx, info), - convert(reset, ctx, info), - convert(init, ctx, info) + extractType(id), + convert(clock, ctx), + convert(reset, ctx), + convert(init, ctx) ) ) - case e @ DefMemory(info, id, t, size) => - Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, false)) - case e @ DefSeqMemory(info, id, t, size, ruw) => - Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, true, ruw)) + case e @ DefMemory(id, t, size) => + Some(firrtl.CDefMemory(fir.NoInfo, e.name, extractType(t), size, false)) + case e @ DefSeqMemory(id, t, size, ruw) => + Some(firrtl.CDefMemory(fir.NoInfo, e.name, extractType(t), size, true, ruw)) case e: DefMemPort[_] => - val info = e.sourceInfo + val info = fir.NoInfo Some( firrtl.CDefMPort( - convert(e.sourceInfo), + fir.NoInfo, e.name, fir.UnknownType, e.source.fullName(ctx), - Seq(convert(e.index, ctx, info), convert(e.clock, ctx, info)), + Seq(convert(e.index, ctx), convert(e.clock, ctx)), convert(e.dir) ) ) - case Connect(info, loc, exp) => - Some(fir.Connect(convert(info), convert(loc, ctx, info), convert(exp, ctx, info))) - case BulkConnect(info, loc, exp) => - Some(fir.PartialConnect(convert(info), convert(loc, ctx, info), convert(exp, ctx, info))) - case Attach(info, locs) => - Some(fir.Attach(convert(info), locs.map(l => convert(l, ctx, info)))) - case DefInvalid(info, arg) => - Some(fir.IsInvalid(convert(info), convert(arg, ctx, info))) - case e @ DefInstance(info, id, _) => - Some(fir.DefInstance(convert(info), e.name, id.name)) - case e @ Printf(_, info, clock, pable) => + case Connect(loc, exp) => + Some(fir.Connect(fir.NoInfo, convert(loc, ctx), convert(exp, ctx))) + case BulkConnect(loc, exp) => + Some(fir.PartialConnect(fir.NoInfo, convert(loc, ctx), convert(exp, ctx))) + case Attach(locs) => + Some(fir.Attach(fir.NoInfo, locs.map(l => convert(l, ctx)))) + case DefInvalid(arg) => + Some(fir.IsInvalid(fir.NoInfo, convert(arg, ctx))) + case e @ DefInstance(id, _) => + Some(fir.DefInstance(fir.NoInfo, e.name, id.name)) + case e @ Printf(_, clock, pable) => val (fmt, args) = unpack(pable, ctx) Some( fir.Print( - convert(info), + fir.NoInfo, fir.StringLit(fmt), - args.map(a => convert(a, ctx, info)), - convert(clock, ctx, info), + args.map(a => convert(a, ctx)), + convert(clock, ctx), firrtl.Utils.one, e.name ) ) - case e @ Verification(_, op, info, clk, pred, msg) => + case e @ Verification(_, op, clk, pred, msg) => val firOp = op match { case Formal.Assert => fir.Formal.Assert case Formal.Assume => fir.Formal.Assume case Formal.Cover => fir.Formal.Cover } - Some( - fir.Verification( - firOp, - convert(info), - convert(clk, ctx, info), - convert(pred, ctx, info), - firrtl.Utils.one, - fir.StringLit(msg), - e.name - ) - ) + None + // Some( + // fir.Verification( + // firOp, + // fir.NoInfo, + // convert(clk, ctx), + // convert(pred, ctx), + // firrtl.Utils.one, + // fir.StringLit(msg), + // e.name + // ) + // ) case _ => None } @@ -236,12 +233,12 @@ private[chisel3] object Converter { // Please see WhenFrame for more details case None => cmd match { - case WhenBegin(info, pred) => - val when = fir.Conditionally(convert(info), convert(pred, ctx, info), fir.EmptyStmt, fir.EmptyStmt) + case WhenBegin(pred) => + val when = fir.Conditionally(fir.NoInfo, convert(pred, ctx), fir.EmptyStmt, fir.EmptyStmt) val frame = WhenFrame(when, stmts, false) stmts = new VectorBuilder[fir.Statement] scope = frame :: scope - case WhenEnd(info, depth, _) => + case WhenEnd(depth, _) => val frame = scope.head val when = if (frame.alt) frame.when.copy(alt = fir.Block(stmts.result())) @@ -258,19 +255,19 @@ private[chisel3] object Converter { // If we're nested we need to add more WhenEnds to ensure each When scope gets // properly closed if (depth > 0) { - nextCmd = WhenEnd(info, depth - 1, false) + nextCmd = WhenEnd(depth - 1, false) } stmts = frame.outer stmts += when scope = scope.tail } - case OtherwiseEnd(info, depth) => + case OtherwiseEnd(depth) => val frame = scope.head val when = frame.when.copy(alt = fir.Block(stmts.result())) // TODO For some reason depth == 1 indicates the last closing otherwise whereas // depth == 0 indicates last closing when if (depth > 1) { - nextCmd = OtherwiseEnd(info, depth - 1) + nextCmd = OtherwiseEnd(depth - 1) } stmts = frame.outer stmts += when @@ -298,9 +295,9 @@ private[chisel3] object Converter { case d => d.specifiedDirection } - def extractType(data: Data, info: SourceInfo): fir.Type = extractType(data, false, info) + def extractType(data: Data): fir.Type = extractType(data, false) - def extractType(data: Data, clearDir: Boolean, info: SourceInfo): fir.Type = data match { + def extractType(data: Data, clearDir: Boolean): fir.Type = data match { case _: Clock => fir.ClockType case _: AsyncReset => fir.AsyncResetType case _: ResetType => fir.ResetType @@ -311,21 +308,21 @@ private[chisel3] object Converter { case d: Vec[_] => val childClearDir = clearDir || d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output - fir.VectorType(extractType(d.sample_element, childClearDir, info), d.length) + fir.VectorType(extractType(d.sample_element, childClearDir), d.length) case d: Record => { val childClearDir = clearDir || d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output def eltField(elt: Data): fir.Field = (childClearDir, firrtlUserDirOf(elt)) match { - case (true, _) => fir.Field(getRef(elt, info).name, fir.Default, extractType(elt, true, info)) + case (true, _) => fir.Field(getRef(elt).name, fir.Default, extractType(elt, true)) case (false, SpecifiedDirection.Unspecified | SpecifiedDirection.Output) => - fir.Field(getRef(elt, info).name, fir.Default, extractType(elt, false, info)) + fir.Field(getRef(elt).name, fir.Default, extractType(elt, false)) case (false, SpecifiedDirection.Flip | SpecifiedDirection.Input) => - fir.Field(getRef(elt, info).name, fir.Flip, extractType(elt, false, info)) + fir.Field(getRef(elt).name, fir.Flip, extractType(elt, false)) } if (!d._isOpaqueType) fir.BundleType(d.elements.toIndexedSeq.reverse.map { case (_, e) => eltField(e) }) else - extractType(d.elements.head._2, childClearDir, info) + extractType(d.elements.head._2, childClearDir) } } @@ -339,9 +336,9 @@ private[chisel3] object Converter { case SpecifiedDirection.Input | SpecifiedDirection.Output => true case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => false } - val info = UnlocatableSourceInfo // Unfortunately there is no source locator for ports ATM - val tpe = extractType(port.id, clearDir, info) - fir.Port(fir.NoInfo, getRef(port.id, info).name, dir, tpe) + + val tpe = extractType(port.id, clearDir) + fir.Port(fir.NoInfo, getRef(port.id).name, dir, tpe) } def convert(component: Component): fir.DefModule = component match { diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index 0e0ebef2..6f993847 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -5,7 +5,6 @@ package chisel3.internal.firrtl import firrtl.{ir => fir} import chisel3._ import chisel3.internal._ -import chisel3.internal.sourceinfo.SourceInfo import chisel3.experimental._ import _root_.firrtl.{ir => firrtlir} import _root_.firrtl.{PrimOps, RenameMap} @@ -294,28 +293,24 @@ object MemPortDirection { object INFER extends MemPortDirection("infer") } -abstract class Command { - def sourceInfo: SourceInfo -} +abstract class Command abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } -case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition -case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command -case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition -case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition -case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition -case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition +case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition +case class DefInvalid(arg: Arg) extends Command +case class DefWire(id: Data) extends Definition +case class DefReg(id: Data, clock: Arg) extends Definition +case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +case class DefMemory(id: HasId, t: Data, size: BigInt) extends Definition case class DefSeqMemory( - sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition case class DefMemPort[T <: Data]( - sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, @@ -323,18 +318,18 @@ case class DefMemPort[T <: Data]( clock: Arg) extends Definition @nowarn("msg=class Port") // delete when Port becomes private -case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition -case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command -case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command -case class AltBegin(sourceInfo: SourceInfo) extends Command -case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command -case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command -case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command -case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +case class DefInstance(id: BaseModule, ports: Seq[Port]) extends Definition +case class WhenBegin(pred: Arg) extends Command +case class WhenEnd(firrtlDepth: Int, hasAlt: Boolean = false) extends Command +case class AltBegin() extends Command +case class OtherwiseEnd(firrtlDepth: Int) extends Command +case class Connect(loc: Node, exp: Arg) extends Command +case class BulkConnect(loc1: Node, loc2: Node) extends Command +case class Attach(locs: Seq[Node]) extends Command +case class ConnectInit(loc: Node, exp: Arg) extends Command case class Port(id: Data, dir: SpecifiedDirection) -case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition +case class Printf(id: printf.Printf, clock: Arg, pable: Printable) extends Definition object Formal extends Enumeration { val Assert = Value("assert") val Assume = Value("assume") diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala index f69c6d04..b417e421 100644 --- a/core/src/main/scala/chisel3/package.scala +++ b/core/src/main/scala/chisel3/package.scala @@ -9,7 +9,6 @@ import chisel3.experimental.BundleLiterals._ /** This package contains the main chisel3 API. */ package object chisel3 { - import internal.sourceinfo.DeprecatedSourceInfo import internal.firrtl.{Port, Width} import internal.Builder |