6 files changed, 27 insertions, 20 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 370a79db..0b05eb69 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -143,7 +143,7 @@ package experimental {
     def widthOf(target:              Data): Width = target.width
     def specifiedDirectionOf(target: Data): SpecifiedDirection = target.specifiedDirection
     def directionOf(target: Data): ActualDirection = {
-      requireIsHardware(target, "node requested directionality on")
+      chisel3.experimental.requireIsHardware(target, "node requested directionality on")
       target.direction
     }
 
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala
index fec02e50..13ddc99d 100644
--- a/core/src/main/scala/chisel3/experimental/Analog.scala
+++ b/core/src/main/scala/chisel3/experimental/Analog.scala
@@ -2,7 +2,7 @@
 
 package chisel3.experimental
 
-import chisel3.internal.firrtl.Width
+import chisel3._
 import chisel3.internal._
 import chisel3.{
   ActualDirection,
diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala
index d07bcf4a..ba54e239 100644
--- a/core/src/main/scala/chisel3/experimental/package.scala
+++ b/core/src/main/scala/chisel3/experimental/package.scala
@@ -13,9 +13,6 @@ package object experimental {
   import scala.language.implicitConversions
   import chisel3.internal.BaseModule
 
-  @deprecated("This type has moved to chisel3", "Chisel 3.5")
-  type ChiselEnum = EnumFactory
-
   // Rocket Chip-style clonemodule
 
   val requireIsHardware = chisel3.internal.requireIsHardware
@@ -25,17 +22,18 @@ package object experimental {
 
   /** Requires that a node is hardware ("bound")
     */
-  object requireIsHardware {
-    def apply(node: Data, msg: String = ""): Unit = {
-      if (!node.isSynthesizable) {
-        val prefix = if (msg.nonEmpty) s"$msg " else ""
-        throw ExpectedHardwareException(
-          s"$prefix'$node' must be hardware, " +
-            "not a bare Chisel type. Perhaps you forgot to wrap it in Wire(_) or IO(_)?"
-        )
-      }
-    }
-  }
+  // readd after replacing references to the one in internal.Binding
+  // object requireIsHardware {
+  //   def apply(node: Data, msg: String = ""): Unit = {
+  //     if (!node.isSynthesizable) {
+  //       val prefix = if (msg.nonEmpty) s"$msg " else ""
+  //       throw ExpectedHardwareException(
+  //         s"$prefix'$node' must be hardware, " +
+  //           "not a bare Chisel type. Perhaps you forgot to wrap it in Wire(_) or IO(_)?"
+  //       )
+  //     }
+  //   }
+  // }
 
   // class dump extends chisel3.internal.naming.dump
   // class treedump extends chisel3.internal.naming.treedump
diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
index 51db0fe7..1078ed10 100644
--- a/core/src/main/scala/chisel3/internal/MonoConnect.scala
+++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -3,7 +3,7 @@
 package chisel3.internal
 
 import chisel3._
-import chisel3.experimental.{Analog, BaseModule, UnsafeEnum}
+import chisel3.experimental.{Analog, BaseModule}
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{Connect, Converter, DefInvalid}
 
diff --git a/core/src/main/scala/chisel3/internal/Warning.scala b/core/src/main/scala/chisel3/internal/Warning.scala
index 5ac506c9..21afc9c5 100644
--- a/core/src/main/scala/chisel3/internal/Warning.scala
+++ b/core/src/main/scala/chisel3/internal/Warning.scala
@@ -27,10 +27,9 @@ private[chisel3] case class Warning(id: WarningID, msg: String)
 private[chisel3] object Warning {
   def apply(id: WarningID, msg: String): Warning = {
     val num = f"[W${id.id}%03d] "
-    new Warning(info, id, num + msg)
+    new Warning(id, num + msg)
   }
   def noInfo(id: WarningID, msg: String): Warning = {
-    implicit val info = SourceInfo.materializeFromStacktrace
     Warning(id, msg)
   }
 }
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index be5fb7b5..203a499a 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -6,6 +6,7 @@ import java.util.{MissingFormatArgumentException, UnknownFormatConversionExcepti
 import chisel3.experimental.VecLiterals._
 import chisel3.experimental.BundleLiterals._
 
+import _root_.firrtl.annotations.{IsMember, Named, ReferenceTarget}
 import scala.collection.mutable
 import scala.annotation.tailrec
 
@@ -13,7 +14,7 @@ import scala.annotation.tailrec
 /** This package contains the main chisel3 API.
   */
 package object chisel3 {
-  import internal.firrtl.{Port, Width}
+  import internal.firrtl.Port
   import internal.Builder
 
   import scala.language.implicitConversions
@@ -191,6 +192,15 @@ package object chisel3 {
     def pathName:       String
     def parentPathName: String
     def parentModName:  String
+
+    /** Returns a FIRRTL Named that refers to this object in the elaborated hardware graph */
+    def toNamed: Named
+
+    /** Returns a FIRRTL IsMember that refers to this object in the elaborated hardware graph */
+    def toTarget: IsMember
+
+    /** Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph */
+    def toAbsoluteTarget: IsMember
   }
 
   @deprecated("MultiIOModule is now just Module", "Chisel 3.5")