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-rw-r--r--core/src/main/scala/chisel3/Aggregate.scala42
-rw-r--r--core/src/main/scala/chisel3/Module.scala27
2 files changed, 31 insertions, 38 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index f22f5e63..b6836ea7 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -936,37 +936,29 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio
}
private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = {
- try {
- _parent.foreach(_.addId(this))
- binding = target
+ _parent.foreach(_.addId(this))
+ binding = target
- val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection)
+ val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection)
- checkForAndReportDuplicates()
+ checkForAndReportDuplicates()
- for ((child, sameChild) <- this.elementsIterator.zip(this.elementsIterator)) {
- if (child != sameChild) {
- throwException(
- s"${this.className} does not return the same objects when calling .elements multiple times. Did you make it a def by mistake?"
- )
- }
- child.bind(ChildBinding(this), resolvedDirection)
+ for ((child, sameChild) <- this.elementsIterator.zip(this.elementsIterator)) {
+ if (child != sameChild) {
+ throwException(
+ s"${this.className} does not return the same objects when calling .elements multiple times. Did you make it a def by mistake?"
+ )
}
+ child.bind(ChildBinding(this), resolvedDirection)
+ }
- // Check that children obey the directionality rules.
- val childDirections = elementsIterator.map(_.direction).toSet - ActualDirection.Empty
- direction = ActualDirection.fromChildren(childDirections, resolvedDirection) match {
- case Some(dir) => dir
- case None =>
- val childWithDirections = getElements.zip(getElements.map(_.direction))
- throw MixedDirectionAggregateException(
- s"Aggregate '$this' can't have elements that are both directioned and undirectioned: $childWithDirections"
- )
- }
- } catch { // nasty compatibility mode shim, where anything flies
- case e: MixedDirectionAggregateException if !compileOptions.dontAssumeDirectionality =>
+ // Check that children obey the directionality rules.
+ val childDirections = elementsIterator.map(_.direction).toSet - ActualDirection.Empty
+ direction = ActualDirection.fromChildren(childDirections, resolvedDirection) match {
+ case Some(dir) => dir
+ case None =>
val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection)
- direction = resolvedDirection match {
+ resolvedDirection match {
case SpecifiedDirection.Unspecified => ActualDirection.Bidirectional(ActualDirection.Default)
case SpecifiedDirection.Flip => ActualDirection.Bidirectional(ActualDirection.Flipped)
case _ => ActualDirection.Bidirectional(ActualDirection.Default)
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 9315a44b..48c33083 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -692,33 +692,34 @@ package experimental {
*/
protected def _bindIoInPlace(iodef: Data): Unit = {
// Compatibility code: Chisel2 did not require explicit direction on nodes
- // (unspecified treated as output, and flip on nothing was input).
- // This sets assigns the explicit directions required by newer semantics on
- // Bundles defined in compatibility mode.
+ // (unspecified treated as output, and flip on nothing was input).
+ // However, we are going to go back to Chisel2 semantics, so we need to make it work
+ // even for chisel3 code.
+ // This assigns the explicit directions required by both semantics on all Bundles.
// This recursively walks the tree, and assigns directions if no explicit
- // direction given by upper-levels (override Input / Output) AND element is
- // directly inside a compatibility Bundle determined by compile options.
- def assignCompatDir(data: Data, insideCompat: Boolean): Unit = {
+ // direction given by upper-levels (override Input / Output)
+ def assignCompatDir(data: Data): Unit = {
data match {
- case data: Element if insideCompat => data._assignCompatibilityExplicitDirection
- case data: Element => // Not inside a compatibility Bundle, nothing to be done
+ case data: Element => data._assignCompatibilityExplicitDirection
case data: Aggregate =>
data.specifiedDirection match {
// Recurse into children to ensure explicit direction set somewhere
case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip =>
data match {
case record: Record =>
- val compatRecord = !record.compileOptions.dontAssumeDirectionality
- record.elementsIterator.foreach(assignCompatDir(_, compatRecord))
+ record.elementsIterator.foreach(assignCompatDir(_))
case vec: Vec[_] =>
- vec.elementsIterator.foreach(assignCompatDir(_, insideCompat))
+ vec.elementsIterator.foreach(assignCompatDir(_))
}
- case SpecifiedDirection.Input | SpecifiedDirection.Output => // forced assign, nothing to do
+ case SpecifiedDirection.Input | SpecifiedDirection.Output =>
+ // forced assign, nothing to do
+ // Note this is because Input and Output recurse down their types to align all fields to that SpecifiedDirection
+ // Thus, no implicit assigment is necessary.
}
}
}
- assignCompatDir(iodef, false)
+ assignCompatDir(iodef)
iodef.bind(PortBinding(this))
_ports += iodef