diff options
Diffstat (limited to 'core/src/main/scala')
29 files changed, 88 insertions, 135 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index fff7a2d0..523d404d 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -20,7 +20,7 @@ class AliasedAggregateFieldException(message: String) extends ChiselException(me * of) other Data objects. */ sealed abstract class Aggregate extends Data { - private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { // scalastyle:ignore cyclomatic.complexity line.size.limit + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { binding = target val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) @@ -117,18 +117,15 @@ trait VecFactory extends SourceInfoDoc { } /** Truncate an index to implement modulo-power-of-2 addressing. */ - private[chisel3] def truncateIndex(idx: UInt, n: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { // scalastyle:ignore line.size.limit - // scalastyle:off if.brace + private[chisel3] def truncateIndex(idx: UInt, n: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { val w = (n-1).bitLength if (n <= 1) 0.U else if (idx.width.known && idx.width.get <= w) idx else if (idx.width.known) idx(w-1,0) else (idx | 0.U(w.W))(w-1,0) - // scalastyle:on if.brace } } -// scalastyle:off line.size.limit /** A vector (array) of [[Data]] elements. Provides hardware versions of various * collection transformation functions found in software array implementations. * @@ -155,7 +152,6 @@ trait VecFactory extends SourceInfoDoc { * - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined) * - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier */ -// scalastyle:on line.size.limit sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extends Aggregate with VecLike[T] { override def toString: String = { @@ -223,7 +219,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] // scalastyle:ignore line.size.limit + def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] /** Strong bulk connect, assigning elements in this Vec from elements in a Seq. * @@ -284,11 +280,9 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) * Results in "Vec(elt0, elt1, ...)" */ def toPrintable: Printable = { - // scalastyle:off if.brace val elts = if (length == 0) List.empty[Printable] else self flatMap (e => List(e.toPrintable, PString(", "))) dropRight 1 - // scalastyle:on if.brace PString("Vec(") + Printables(elts) + PString(")") } @@ -391,7 +385,7 @@ object VecInit extends SourceInfoDoc { def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate /** @group SourceInfoTransformMacro */ - def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = // scalastyle:ignore line.size.limit + def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = apply((0 until n).map(i => gen(i))) } @@ -519,7 +513,7 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio * ) * }}} */ - private[chisel3] def _makeLit(elems: (this.type => (Data, Data))*): this.type = { // scalastyle:ignore line.size.limit method.length method.name cyclomatic.complexity + private[chisel3] def _makeLit(elems: (this.type => (Data, Data))*): this.type = { // Returns pairs of all fields, element-level and containers, in a Record and their path names def getRecursiveFields(data: Data, path: String): Seq[(Data, String)] = data match { case data: Record => data.elements.map { case (fieldName, fieldData) => @@ -640,7 +634,7 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio } // NOTE: This sets up dependent references, it can be done before closing the Module - private[chisel3] override def _onModuleClose: Unit = { // scalastyle:ignore method.name + private[chisel3] override def _onModuleClose: Unit = { // Since Bundle names this via reflection, it is impossible for two elements to have the same // identifier; however, Namespace sanitizes identifiers to make them legal for Firrtl/Verilog // which can cause collisions @@ -654,13 +648,11 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio // Helper because Bundle elements are reversed before printing private[chisel3] def toPrintableHelper(elts: Seq[(String, Data)]): Printable = { - // scalastyle:off if.brace val xs = if (elts.isEmpty) List.empty[Printable] // special case because of dropRight below else elts flatMap { case (name, data) => List(PString(s"$name -> "), data.toPrintable, PString(", ")) } dropRight 1 // Remove trailing ", " - // scalastyle:on if.brace PString(s"$className(") + Printables(xs) + PString(")") } /** Default "pretty-print" implementation @@ -778,7 +770,6 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { } } ListMap(nameMap.toSeq sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }: _*) - // scalastyle:ignore method.length } /** @@ -805,7 +796,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { private val _containingModule: Option[BaseModule] = Builder.currentModule private val _containingBundles: Seq[Bundle] = Builder.updateBundleStack(this) - override def cloneType : this.type = { // scalastyle:ignore cyclomatic.complexity method.length + override def cloneType : this.type = { // This attempts to infer constructor and arguments to clone this Bundle subtype without // requiring the user explicitly overriding cloneType. import scala.language.existentials @@ -901,7 +892,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { Some(ctor.newInstance().asInstanceOf[this.type]) case (argType :: Nil, Some((_, outerInstance))) => if (outerInstance == null) { - Builder.deprecated(s"chisel3.1 autoclonetype failed, falling back to 3.0 behavior using null as the outer instance." + // scalastyle:ignore line.size.limit + Builder.deprecated(s"chisel3.1 autoclonetype failed, falling back to 3.0 behavior using null as the outer instance." + s" Autoclonetype failure reason: ${outerClassError.get}", Some(s"$clazz")) Some(ctor.newInstance(outerInstance).asInstanceOf[this.type]) @@ -925,7 +916,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { // Get constructor parameters and accessible fields val classSymbol = classSymbolOption.getOrElse(autoClonetypeError(s"scala reflection failed." + " This is known to occur with inner classes on anonymous outer classes." + - " In those cases, autoclonetype only works with no-argument constructors, or you can define a custom cloneType.")) // scalastyle:ignore line.size.limit + " In those cases, autoclonetype only works with no-argument constructors, or you can define a custom cloneType.")) val decls = classSymbol.typeSignature.decls val ctors = decls.collect { case meth: MethodSymbol if meth.isConstructor => meth } @@ -977,10 +968,8 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { val accessorsName = accessors.filter(_.isStable).map(_.name.toString) val paramsDiff = ctorParamsNames.toSet -- accessorsName.toSet if (!paramsDiff.isEmpty) { - // scalastyle:off line.size.limit autoClonetypeError(s"constructor has parameters (${paramsDiff.toList.sorted.mkString(", ")}) that are not both immutable and accessible." + " Either make all parameters immutable and accessible (vals) so cloneType can be inferred, or define a custom cloneType method.") - // scalastyle:on line.size.limit } // Get all the argument values @@ -997,10 +986,8 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { case (paramName, paramVal: Data) if paramVal.topBindingOpt.isDefined => paramName } if (boundDataParamNames.nonEmpty) { - // scalastyle:off line.size.limit autoClonetypeError(s"constructor parameters (${boundDataParamNames.sorted.mkString(", ")}) have values that are hardware types, which is likely to cause subtle errors." + " Use chisel types instead: use the value before it is turned to a hardware type (with Wire(...), Reg(...), etc) or use chiselTypeOf(...) to extract the chisel type.") - // scalastyle:on line.size.limit } // Clone unbound parameters in case they are being used as bundle fields. @@ -1033,6 +1020,4 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { * the fields in the order they were defined */ override def toPrintable: Printable = toPrintableHelper(elements.toList.reverse) - // scalastyle:off method.length } -// scalastyle:off file.size.limit diff --git a/core/src/main/scala/chisel3/Annotation.scala b/core/src/main/scala/chisel3/Annotation.scala index e54b1bf9..104fc575 100644 --- a/core/src/main/scala/chisel3/Annotation.scala +++ b/core/src/main/scala/chisel3/Annotation.scala @@ -39,7 +39,7 @@ final case class ChiselLegacyAnnotation private[chisel3] ( } private[chisel3] object ChiselLegacyAnnotation -object annotate { // scalastyle:ignore object.name +object annotate { def apply(anno: ChiselAnnotation): Unit = { Builder.annotations += anno } @@ -82,7 +82,7 @@ object annotate { // scalastyle:ignore object.name * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically. */ -object doNotDedup { // scalastyle:ignore object.name +object doNotDedup { /** Marks a module to be ignored in Dedup Transform in Firrtl * * @param module The module to be marked diff --git a/core/src/main/scala/chisel3/Assert.scala b/core/src/main/scala/chisel3/Assert.scala index af58bce6..310a454d 100644 --- a/core/src/main/scala/chisel3/Assert.scala +++ b/core/src/main/scala/chisel3/Assert.scala @@ -10,7 +10,7 @@ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.SourceInfo -object assert { // scalastyle:ignore object.name +object assert { /** Checks for a condition to be valid in the circuit at all times. If the * condition evaluates to false, the circuit simulation stops with an error. * @@ -32,10 +32,10 @@ object assert { // scalastyle:ignore object.name * that */ // Macros currently can't take default arguments, so we need two functions to emulate defaults. - def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl_msg_data // scalastyle:ignore line.size.limit + def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl_msg_data def apply(cond: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl - def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree, compileOptions: c.Tree): c.Tree = { // scalastyle:ignore line.size.limit + def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree, compileOptions: c.Tree): c.Tree = { import c.universe._ val p = c.enclosingPosition val condStr = s"${p.source.file.name}:${p.line} ${p.lineContent.trim}" @@ -51,7 +51,7 @@ object assert { // scalastyle:ignore object.name q"$apply_impl_do($cond, $condStr, _root_.scala.None)($sourceInfo, $compileOptions)" } - def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { // scalastyle:ignore line.size.limit + def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { val escLine = line.replaceAll("%", "%%") when (!(cond || Module.reset.asBool)) { val fmt = message match { @@ -77,7 +77,7 @@ object assert { // scalastyle:ignore object.name } } -object stop { // scalastyle:ignore object.name +object stop { /** Terminate execution with a failure code. */ def apply(code: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { when (!Module.reset.asBool) { diff --git a/core/src/main/scala/chisel3/Attach.scala b/core/src/main/scala/chisel3/Attach.scala index 25c83d9a..2736ed65 100644 --- a/core/src/main/scala/chisel3/Attach.scala +++ b/core/src/main/scala/chisel3/Attach.scala @@ -8,10 +8,10 @@ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.SourceInfo -object attach { // scalastyle:ignore object.name +object attach { // Exceptions that can be generated by attach case class AttachException(message: String) extends ChiselException(message) - def ConditionalAttachException: AttachException = // scalastyle:ignore method.name + def ConditionalAttachException: AttachException = AttachException(": Conditional attach is not allowed!") // Actual implementation diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala index 43c34d9d..0d6ebca7 100644 --- a/core/src/main/scala/chisel3/Bits.scala +++ b/core/src/main/scala/chisel3/Bits.scala @@ -14,7 +14,6 @@ import chisel3.internal.firrtl.PrimOp._ import _root_.firrtl.{ir => firrtlir} import _root_.firrtl.{constraint => firrtlconstraint} -// scalastyle:off method.name line.size.limit file.size.limit /** Exists to unify common interfaces of [[Bits]] and [[Reset]]. * @@ -49,7 +48,7 @@ private[chisel3] sealed trait ToBoolable extends Element { * @define sumWidth @note The width of the returned $coll is `width of this` + `width of that`. * @define unchangedWidth @note The width of the returned $coll is unchanged, i.e., the `width of this`. */ -sealed abstract class Bits(private[chisel3] val width: Width) extends Element with ToBoolable { //scalastyle:off number.of.methods +sealed abstract class Bits(private[chisel3] val width: Width) extends Element with ToBoolable { // TODO: perhaps make this concrete? // Arguments for: self-checking code (can't do arithmetic on bits) // Arguments against: generates down to a FIRRTL UInt anyways @@ -1212,7 +1211,6 @@ package experimental { */ def litToBigDecimal: BigDecimal = litToBigDecimalOption.get } - //scalastyle:off number.of.methods /** A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point * may be inferred. * @@ -1625,7 +1623,6 @@ package experimental { } } - //scalastyle:off number.of.methods cyclomatic.complexity /** * A sealed class representing a fixed point number that has a range, an additional * parameter that can determine a minimum and maximum supported value. @@ -1657,7 +1654,6 @@ package experimental { private[chisel3] override def cloneTypeWidth(w: Width): this.type = new Interval(range).asInstanceOf[this.type] - //scalastyle:off cyclomatic.complexity def toType: String = { val zdec1 = """([+\-]?[0-9]\d*)(\.[0-9]*[1-9])(0*)""".r val zdec2 = """([+\-]?[0-9]\d*)(\.0*)""".r diff --git a/core/src/main/scala/chisel3/BlackBox.scala b/core/src/main/scala/chisel3/BlackBox.scala index f29962d7..8c5138d5 100644 --- a/core/src/main/scala/chisel3/BlackBox.scala +++ b/core/src/main/scala/chisel3/BlackBox.scala @@ -132,11 +132,11 @@ package experimental { * }}} * @note The parameters API is experimental and may change */ -abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox { // scalastyle:ignore line.size.limit +abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox { def io: Record // Allow access to bindings from the compatibility package - protected def _compatIoPortBound() = portsContains(io) // scalastyle:ignore method.name + protected def _compatIoPortBound() = portsContains(io) private[chisel3] override def generateComponent(): Component = { _compatAutoWrapPorts() // pre-IO(...) compatibility hack diff --git a/core/src/main/scala/chisel3/BoolFactory.scala b/core/src/main/scala/chisel3/BoolFactory.scala index bccd6414..78e73156 100644 --- a/core/src/main/scala/chisel3/BoolFactory.scala +++ b/core/src/main/scala/chisel3/BoolFactory.scala @@ -4,7 +4,6 @@ package chisel3 import chisel3.internal.firrtl.{ULit, Width} -// scalastyle:off method.name trait BoolFactory { /** Creates an empty Bool. diff --git a/core/src/main/scala/chisel3/Clock.scala b/core/src/main/scala/chisel3/Clock.scala index d7975b1e..c5154a8b 100644 --- a/core/src/main/scala/chisel3/Clock.scala +++ b/core/src/main/scala/chisel3/Clock.scala @@ -21,7 +21,7 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element private[chisel3] def typeEquivalent(that: Data): Boolean = this.getClass == that.getClass - override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { // scalastyle:ignore line.size.limit + override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions) case _ => super.badConnect(that)(sourceInfo) } @@ -35,7 +35,7 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element final def asBool(): Bool = macro SourceInfoTransform.noArg def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt().asBool() - override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit + override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { this := that.asBool.asClock diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index 93fccaec..46c98bae 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -166,7 +166,7 @@ package experimental { } // Internal reflection-style APIs, subject to change and removal whenever. - object internal { // scalastyle:ignore object.name + object internal { def isSynthesizable(target: Data): Boolean = target.isSynthesizable // For those odd cases where you need to care about object reference and uniqueness def chiselTypeClone[T<:Data](target: Data): T = { @@ -182,7 +182,6 @@ package experimental { * - For other types of the same class are are the same: clone of any of the elements * - Otherwise: fail */ -//scalastyle:off cyclomatic.complexity private[chisel3] object cloneSupertype { def apply[T <: Data](elts: Seq[T], createdType: String)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { @@ -273,7 +272,7 @@ object Flipped { * @groupdesc Connect Utilities for connecting hardware components * @define coll data */ -abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // scalastyle:ignore number.of.methods +abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // This is a bad API that punches through object boundaries. @deprecated("pending removal once all instances replaced", "chisel3") private[chisel3] def flatten: IndexedSeq[Element] = { @@ -303,7 +302,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc * the compatibility layer where, at the elements, Flip is Input and unspecified is Output. * DO NOT USE OUTSIDE THIS PURPOSE. THIS OPERATION IS DANGEROUS! */ - private[chisel3] def _assignCompatibilityExplicitDirection: Unit = { // scalastyle:off method.name + private[chisel3] def _assignCompatibilityExplicitDirection: Unit = { (this, _specifiedDirection) match { case (_: Analog, _) => // nothing to do case (_, SpecifiedDirection.Unspecified) => _specifiedDirection = SpecifiedDirection.Output @@ -391,7 +390,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc private[chisel3] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = throwException(s"cannot connect ${this} and ${that}") - private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit + private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { if (connectCompileOptions.checkSynthesizable) { requireIsHardware(this, "data to be connected") requireIsHardware(that, "data to be connected") @@ -411,7 +410,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc this legacyConnect that } } - private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit + private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { if (connectCompileOptions.checkSynthesizable) { requireIsHardware(this, s"data to be bulk-connected") requireIsHardware(that, s"data to be bulk-connected") @@ -443,7 +442,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc private[chisel3] def lref: Node = { requireIsHardware(this) topBindingOpt match { - case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding") // scalastyle:ignore line.size.limit + case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding") case Some(binding: TopBinding) => Node(this) case opt => throwException(s"internal error: unknown binding $opt in generating LHS ref") } @@ -491,7 +490,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc * @param that the $coll to connect to * @group Connect */ - final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) // scalastyle:ignore line.size.limit + final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) /** Connect this $coll to that $coll bi-directionally and element-wise. * @@ -500,7 +499,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc * @param that the $coll to connect to * @group Connect */ - final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) // scalastyle:ignore line.size.limit + final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) @chiselRuntimeDeprecated @deprecated("litArg is deprecated, use litOption or litTo*Option", "3.2") @@ -674,7 +673,7 @@ object Wire extends WireFactory */ object WireDefault { - private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { // scalastyle:ignore line.size.limit + private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { implicit val noSourceInfo = UnlocatableSourceInfo val x = Wire(t) requireIsHardware(init, "wire initializer") @@ -687,7 +686,7 @@ object WireDefault { * @param init The default connection to this [[Wire]], can only be [[DontCare]] * @note This is really just a specialized form of `apply[T <: Data](t: T, init: T): T` with [[DontCare]] as `init` */ - def apply[T <: Data](t: T, init: DontCare.type)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { // scalastyle:ignore line.size.limit + def apply[T <: Data](t: T, init: DontCare.type)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { applyImpl(t, init) } @@ -732,11 +731,11 @@ package internal { def toPrintable: Printable = PString("DONTCARE") - private[chisel3] def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit + private[chisel3] def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)") } - def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): UInt = { // scalastyle:ignore line.size.limit + def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): UInt = { Builder.error("DontCare does not have a UInt representation") 0.U } diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index f1c4e30a..140e3003 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -250,7 +250,7 @@ package experimental { Builder.globalNamespace.name(desiredName) } catch { case e: NullPointerException => throwException( - s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e) // scalastyle:ignore line.size.limit + s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e) case t: Throwable => throw t } @@ -329,12 +329,12 @@ package experimental { * * TODO: remove this, perhaps by removing Bindings checks in compatibility mode. */ - def _compatAutoWrapPorts() {} // scalastyle:ignore method.name + def _compatAutoWrapPorts() {} /** Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to * io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO. */ - protected def _bindIoInPlace(iodef: Data): Unit = { // scalastyle:ignore method.name + protected def _bindIoInPlace(iodef: Data): Unit = { // Compatibility code: Chisel2 did not require explicit direction on nodes // (unspecified treated as output, and flip on nothing was input). // This sets assigns the explicit directions required by newer semantics on @@ -385,7 +385,7 @@ package experimental { * TODO(twigg): Specifically walk the Data definition to call out which nodes * are problematic. */ - protected def IO[T <: Data](iodef: T): T = chisel3.experimental.IO.apply(iodef) // scalastyle:ignore method.name + protected def IO[T <: Data](iodef: T): T = chisel3.experimental.IO.apply(iodef) // // Internal Functions diff --git a/core/src/main/scala/chisel3/MultiClock.scala b/core/src/main/scala/chisel3/MultiClock.scala index 239e745a..718dc989 100644 --- a/core/src/main/scala/chisel3/MultiClock.scala +++ b/core/src/main/scala/chisel3/MultiClock.scala @@ -6,7 +6,7 @@ import chisel3.internal._ import scala.language.experimental.macros -object withClockAndReset { // scalastyle:ignore object.name +object withClockAndReset { /** Creates a new Clock and Reset scope * * @param clock the new implicit Clock @@ -31,7 +31,7 @@ object withClockAndReset { // scalastyle:ignore object.name } } -object withClock { // scalastyle:ignore object.name +object withClock { /** Creates a new Clock scope * * @param clock the new implicit Clock @@ -49,7 +49,7 @@ object withClock { // scalastyle:ignore object.name } } -object withReset { // scalastyle:ignore object.name +object withReset { /** Creates a new Reset scope * * @param reset the new implicit Reset diff --git a/core/src/main/scala/chisel3/Num.scala b/core/src/main/scala/chisel3/Num.scala index 7a6b0744..893dd1ce 100644 --- a/core/src/main/scala/chisel3/Num.scala +++ b/core/src/main/scala/chisel3/Num.scala @@ -8,7 +8,6 @@ import chisel3.internal.firrtl.{BinaryPoint, KnownBinaryPoint} import scala.language.experimental.macros import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform} -// scalastyle:off method.name // REVIEW TODO: Further discussion needed on what Num actually is. diff --git a/core/src/main/scala/chisel3/Printable.scala b/core/src/main/scala/chisel3/Printable.scala index 7add9166..7b730617 100644 --- a/core/src/main/scala/chisel3/Printable.scala +++ b/core/src/main/scala/chisel3/Printable.scala @@ -60,7 +60,7 @@ sealed abstract class Printable { object Printable { /** Pack standard printf fmt, args* style into Printable */ - def pack(fmt: String, data: Data*): Printable = { // scalastyle:ignore method.length + def pack(fmt: String, data: Data*): Printable = { val args = data.toIterator // Error handling diff --git a/core/src/main/scala/chisel3/Printf.scala b/core/src/main/scala/chisel3/Printf.scala index 0478e889..fb525b6e 100644 --- a/core/src/main/scala/chisel3/Printf.scala +++ b/core/src/main/scala/chisel3/Printf.scala @@ -13,7 +13,7 @@ import chisel3.internal.sourceinfo.SourceInfo * * See apply methods for use */ -object printf { // scalastyle:ignore object.name +object printf { /** Helper for packing escape characters */ private[chisel3] def format(formatIn: String): String = { require(formatIn forall (c => c.toInt > 0 && c.toInt < 128), @@ -93,10 +93,10 @@ object printf { // scalastyle:ignore object.name } } - private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit + private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { val clock = Builder.forcedClock pushCommand(Printf(sourceInfo, clock.ref, pable)) } - private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = // scalastyle:ignore line.size.limit + private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = printfWithoutReset(Printable.pack(fmt, data:_*)) } diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 218022cc..0fcec266 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -58,7 +58,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) } - private[chisel3] override def generateComponent(): Component = { // scalastyle:ignore cyclomatic.complexity + private[chisel3] override def generateComponent(): Component = { require(!_closed, "Can't generate module more than once") _closed = true @@ -194,7 +194,7 @@ package internal { def io: Record // Allow access to bindings from the compatibility package - protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name + protected def _compatIoPortBound() = portsContains(io) private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = { for (port <- getModulePorts) { @@ -211,7 +211,7 @@ package internal { // Restrict IO to just io, clock, and reset require(io != null, "Module must have io") require(portsContains(io), "Module must have io wrapped in IO(...)") - require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") // scalastyle:ignore line.size.limit + require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") require(portsSize == 3, "Module must only have io, clock, and reset as IO") super.generateComponent() diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala index c1c6b1db..35bab7c2 100644 --- a/core/src/main/scala/chisel3/SIntFactory.scala +++ b/core/src/main/scala/chisel3/SIntFactory.scala @@ -16,7 +16,6 @@ trait SIntFactory { } /** Create an SInt literal with specified width. */ - // scalastyle:off method.name protected[chisel3] def Lit(value: BigInt, width: Width): SInt = { val lit = SLit(value, width) val result = new SInt(lit.width) diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala index 28f753b1..9f09b2c2 100644 --- a/core/src/main/scala/chisel3/SeqUtils.scala +++ b/core/src/main/scala/chisel3/SeqUtils.scala @@ -8,7 +8,6 @@ import chisel3.internal.throwException import scala.language.experimental.macros import chisel3.internal.sourceinfo._ -//scalastyle:off method.name private[chisel3] object SeqUtils { /** Concatenates the data elements of the input sequence, in sequence order, together. @@ -65,7 +64,6 @@ private[chisel3] object SeqUtils { */ def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro SourceInfoTransform.inArg - //scalastyle:off method.length cyclomatic.complexity /** @group SourceInfoTransformMacros */ def do_oneHotMux[T <: Data](in: Iterable[(Bool, T)]) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { diff --git a/core/src/main/scala/chisel3/StrongEnum.scala b/core/src/main/scala/chisel3/StrongEnum.scala index 8edce4d8..5414ba40 100644 --- a/core/src/main/scala/chisel3/StrongEnum.scala +++ b/core/src/main/scala/chisel3/StrongEnum.scala @@ -115,14 +115,12 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea final def > (that: EnumType): Bool = macro SourceInfoTransform.thatArg final def >= (that: EnumType): Bool = macro SourceInfoTransform.thatArg - // scalastyle:off line.size.limit method.name def do_=== (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, EqualOp, that) def do_=/= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, NotEqualOp, that) def do_< (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, LessOp, that) def do_> (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, GreaterOp, that) def do_<= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, LessEqOp, that) def do_>= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, GreaterEqOp, that) - // scalastyle:on line.size.limit method.name override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(width), AsUIntOp, ref)) @@ -246,8 +244,8 @@ abstract class EnumFactory { enum_records.find(_.inst.litValue() == id).map(_.name) } - protected def Value: Type = macro EnumMacros.ValImpl // scalastyle:off method.name - protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl // scalastyle:off method.name + protected def Value: Type = macro EnumMacros.ValImpl + protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl protected def do_Value(name: String): Type = { val result = new Type @@ -280,7 +278,6 @@ abstract class EnumFactory { def apply(): Type = new Type def apply(n: UInt)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Type = { - // scalastyle:off line.size.limit if (n.litOption.isDefined) { enumInstances.find(_.litValue == n.litValue) match { case Some(result) => result @@ -300,12 +297,11 @@ abstract class EnumFactory { result } } - // scalastyle:on line.size.limit } private[chisel3] object EnumMacros { - def ValImpl(c: Context) : c.Tree = { // scalastyle:off method.name + def ValImpl(c: Context) : c.Tree = { import c.universe._ // Much thanks to michael_s for this solution: @@ -320,7 +316,7 @@ private[chisel3] object EnumMacros { q"""this.do_Value($name)""" } - def ValCustomImpl(c: Context)(id: c.Expr[UInt]): c.universe.Tree = { // scalastyle:off method.name + def ValCustomImpl(c: Context)(id: c.Expr[UInt]): c.universe.Tree = { import c.universe._ val term = c.internal.enclosingOwner diff --git a/core/src/main/scala/chisel3/UIntFactory.scala b/core/src/main/scala/chisel3/UIntFactory.scala index 3868962b..864e6cb8 100644 --- a/core/src/main/scala/chisel3/UIntFactory.scala +++ b/core/src/main/scala/chisel3/UIntFactory.scala @@ -15,7 +15,6 @@ trait UIntFactory { def apply(width: Width): UInt = new UInt(width) /** Create a UInt literal with specified width. */ - // scalastyle:off method.name protected[chisel3] def Lit(value: BigInt, width: Width): UInt = { val lit = ULit(value, width) val result = new UInt(lit.width) @@ -24,7 +23,6 @@ trait UIntFactory { } /** Create a UInt with the specified range, validate that range is effectively > 0 */ - //scalastyle:off cyclomatic.complexity def apply(range: IntervalRange): UInt = { // Check is only done against lower bound because range will already insist that range high >= low range.lowerBound match { diff --git a/core/src/main/scala/chisel3/When.scala b/core/src/main/scala/chisel3/When.scala index ea243bbe..b24bdb35 100644 --- a/core/src/main/scala/chisel3/When.scala +++ b/core/src/main/scala/chisel3/When.scala @@ -9,7 +9,7 @@ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo} -object when { // scalastyle:ignore object.name +object when { /** Create a `when` condition block, where whether a block of logic is * executed or not depends on the conditional. * @@ -28,7 +28,7 @@ object when { // scalastyle:ignore object.name * }}} */ - def apply(cond: => Bool)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { // scalastyle:ignore line.size.limit + def apply(cond: => Bool)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { new WhenContext(sourceInfo, Some(() => cond), block) } } @@ -51,7 +51,7 @@ final class WhenContext(sourceInfo: SourceInfo, cond: Option[() => Bool], block: * declaration and assignment of the Bool node of the predicate in * the correct place. */ - def elsewhen (elseCond: => Bool)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { // scalastyle:ignore line.size.limit + def elsewhen (elseCond: => Bool)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { new WhenContext(sourceInfo, Some(() => elseCond), block, firrtlDepth + 1) } diff --git a/core/src/main/scala/chisel3/dontTouch.scala b/core/src/main/scala/chisel3/dontTouch.scala index 5dfd9f19..a0c5dcc9 100644 --- a/core/src/main/scala/chisel3/dontTouch.scala +++ b/core/src/main/scala/chisel3/dontTouch.scala @@ -20,7 +20,7 @@ import firrtl.transforms.DontTouchAnnotation * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically. */ -object dontTouch { // scalastyle:ignore object.name +object dontTouch { /** Marks a signal to be preserved in Chisel and Firrtl * * @note Requires the argument to be bound to hardware diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala index 0c0b4490..da103318 100644 --- a/core/src/main/scala/chisel3/experimental/package.scala +++ b/core/src/main/scala/chisel3/experimental/package.scala @@ -7,7 +7,7 @@ package chisel3 * Because its contents won't necessarily have the same level of stability and support as * non-experimental, you must explicitly import this package to use its contents. */ -package object experimental { // scalastyle:ignore object.name +package object experimental { import scala.language.implicitConversions import chisel3.internal.BaseModule @@ -44,7 +44,7 @@ package object experimental { // scalastyle:ignore object.name * q2_io.enq <> q1.io.deq * }}} */ - def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): ClonePorts = { // scalastyle:ignore line.size.limit + def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): ClonePorts = { BaseModule.cloneIORecord(proto) } } @@ -69,8 +69,8 @@ package object experimental { // scalastyle:ignore object.name def range(args: Any*): chisel3.internal.firrtl.IntervalRange = macro chisel3.internal.RangeTransform.apply } - class dump extends chisel3.internal.naming.dump // scalastyle:ignore class.name - class treedump extends chisel3.internal.naming.treedump // scalastyle:ignore class.name + class dump extends chisel3.internal.naming.dump + class treedump extends chisel3.internal.naming.treedump /** Experimental macro for naming Chisel hardware values * * By default, Chisel uses reflection for naming which only works for public fields of `Bundle` @@ -96,7 +96,7 @@ package object experimental { // scalastyle:ignore object.name * } * }}} */ - class chiselName extends chisel3.internal.naming.chiselName // scalastyle:ignore class.name + class chiselName extends chisel3.internal.naming.chiselName /** Do not name instances of this type in [[chiselName]] * * By default, `chiselName` will include `val` names of instances of annotated classes as a @@ -131,7 +131,6 @@ package object experimental { // scalastyle:ignore object.name object BundleLiterals { implicit class AddBundleLiteralConstructor[T <: Record](x: T) { - //scalastyle:off method.name def Lit(elems: (T => (Data, Data))*): T = { x._makeLit(elems: _*) } diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala index 6b4c1070..8cc4bbaf 100644 --- a/core/src/main/scala/chisel3/internal/BiConnect.scala +++ b/core/src/main/scala/chisel3/internal/BiConnect.scala @@ -24,7 +24,6 @@ import chisel3.internal.sourceinfo._ */ private[chisel3] object BiConnect { - // scalastyle:off method.name public.methods.have.type // These are all the possible exceptions that can be thrown. // These are from element-level connection def BothDriversException = @@ -48,7 +47,6 @@ private[chisel3] object BiConnect { BiConnectException(sourceInfo.makeMessage(": Analog previously bulk connected at " + _)) def DontCareCantBeSink = BiConnectException(": DontCare cannot be a connection sink (LHS)") - // scalastyle:on method.name public.methods.have.type /** This function is what recursively tries to connect a left and right together * @@ -56,7 +54,7 @@ private[chisel3] object BiConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit cyclomatic.complexity method.length + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { (left, right) match { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => @@ -217,7 +215,7 @@ private[chisel3] object BiConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit cyclomatic.complexity method.length + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If left or right have no location, assume in context module // This can occur if one of them is a literal, unbound will error previously diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala index bacc9fee..510919bc 100644 --- a/core/src/main/scala/chisel3/internal/Builder.scala +++ b/core/src/main/scala/chisel3/internal/Builder.scala @@ -78,7 +78,7 @@ trait InstanceId { } private[chisel3] trait HasId extends InstanceId { - private[chisel3] def _onModuleClose: Unit = {} // scalastyle:ignore method.name + private[chisel3] def _onModuleClose: Unit = {} private[chisel3] val _parent: Option[BaseModule] = Builder.currentModule _parent.foreach(_.addId(this)) @@ -222,7 +222,6 @@ private[chisel3] class DynamicContext() { val namingStack = new NamingStack } -//scalastyle:off number.of.methods private[chisel3] object Builder { // All global mutable state must be referenced via dynamicContextVar!! private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None) @@ -288,7 +287,7 @@ private[chisel3] object Builder { case other => module } case _ => throwException( - "Error: Not in a RawModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // scalastyle:ignore line.size.limit + "Error: Not in a RawModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // A bare api call is, e.g. calling Wire() from the scala console). ) } @@ -296,7 +295,7 @@ private[chisel3] object Builder { def forcedUserModule: RawModule = currentModule match { case Some(module: RawModule) => module case _ => throwException( - "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // scalastyle:ignore line.size.limit + "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // A bare api call is, e.g. calling Wire() from the scala console). ) } diff --git a/core/src/main/scala/chisel3/internal/Error.scala b/core/src/main/scala/chisel3/internal/Error.scala index 369da52e..89d6cc63 100644 --- a/core/src/main/scala/chisel3/internal/Error.scala +++ b/core/src/main/scala/chisel3/internal/Error.scala @@ -75,7 +75,7 @@ class ChiselException(message: String, cause: Throwable = null) extends Exceptio sw.write(likelyCause.toString + "\n") sw.write("\t...\n") trimmed.foreach(ste => sw.write(s"\tat $ste\n")) - sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") // scalastyle:ignore line.size.limit + sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") sw.toString } } @@ -103,7 +103,7 @@ private[chisel3] class ErrorLog { /** Emit an informational message */ def info(m: String): Unit = - println(new Info("[%2.3f] %s".format(elapsedTime/1e3, m), None)) // scalastyle:ignore regex + println(new Info("[%2.3f] %s".format(elapsedTime/1e3, m), None)) /** Log a deprecation warning message */ def deprecated(m: => String, location: Option[String]): Unit = { @@ -121,7 +121,6 @@ private[chisel3] class ErrorLog { /** Throw an exception if any errors have yet occurred. */ def checkpoint(): Unit = { - // scalastyle:off line.size.limit regex deprecations.foreach { case ((message, sourceLoc), count) => println(s"${ErrorLog.depTag} $sourceLoc ($count calls): $message") } @@ -154,7 +153,6 @@ private[chisel3] class ErrorLog { // No fatal errors, clear accumulated warnings since they've been reported errors.clear() } - // scalastyle:on line.size.limit regex } /** Returns the best guess at the first stack frame that belongs to user code. diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala index 41402021..24c0e229 100644 --- a/core/src/main/scala/chisel3/internal/MonoConnect.scala +++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala @@ -34,7 +34,6 @@ import chisel3.internal.sourceinfo.SourceInfo */ private[chisel3] object MonoConnect { - // scalastyle:off method.name public.methods.have.type // These are all the possible exceptions that can be thrown. // These are from element-level connection def UnreadableSourceException = @@ -58,7 +57,6 @@ private[chisel3] object MonoConnect { MonoConnectException(": Analog cannot participate in a mono connection (source - RHS)") def AnalogMonoConnectionException = MonoConnectException(": Analog cannot participate in a mono connection (source and sink)") - // scalastyle:on method.name public.methods.have.type /** This function is what recursively tries to connect a sink and source together * @@ -66,7 +64,7 @@ private[chisel3] object MonoConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect( //scalastyle:off cyclomatic.complexity method.length + def connect( sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Data, @@ -176,7 +174,7 @@ private[chisel3] object MonoConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If source has no location, assume in context module // This can occur if is a literal, unbound will error previously @@ -215,7 +213,7 @@ private[chisel3] object MonoConnect { throw UnreadableSourceException } } - case (Input, Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) // scalastyle:ignore line.size.limit + case (Input, Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) case (Input, _) => throw UnwritableSinkException } } diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index 5c1d6935..67d87a68 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -41,7 +41,7 @@ private[chisel3] object Converter { // TODO // * Memoize? // * Move into the Chisel IR? - def convert(arg: Arg, ctx: Component): fir.Expression = arg match { // scalastyle:ignore cyclomatic.complexity + def convert(arg: Arg, ctx: Component): fir.Expression = arg match { case Node(id) => convert(id.getRef, ctx) case Ref(name) => @@ -53,10 +53,8 @@ private[chisel3] object Converter { case Index(imm, value) => fir.SubAccess(convert(imm, ctx), convert(value, ctx), fir.UnknownType) case ModuleIO(mod, name) => - // scalastyle:off if.brace if (mod eq ctx.id) fir.Reference(name, fir.UnknownType) else fir.SubField(fir.Reference(mod.getRef.name, fir.UnknownType), name, fir.UnknownType) - // scalastyle:on if.brace case u @ ULit(n, UnknownWidth()) => fir.UIntLiteral(n, fir.IntWidth(u.minWidth)) case ULit(n, w) => @@ -81,7 +79,7 @@ private[chisel3] object Converter { } /** Convert Commands that map 1:1 to Statements */ - def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { // scalastyle:ignore cyclomatic.complexity line.size.limit + def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { case e: DefPrim[_] => val consts = e.args.collect { case ILit(i) => i } val args = e.args.flatMap { @@ -151,9 +149,8 @@ private[chisel3] object Converter { * @param ctx Component (Module) context within which we are translating * @return FIRRTL Statement that is equivalent to the input cmds */ - def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { // scalastyle:ignore cyclomatic.complexity + def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { @tailrec - // scalastyle:off if.brace def rec(acc: Queue[fir.Statement], scope: List[WhenFrame]) (cmds: Seq[Command]): Seq[fir.Statement] = { @@ -197,7 +194,6 @@ private[chisel3] object Converter { } } } - // scalastyle:on if.brace fir.Block(rec(Queue.empty, List.empty)(cmds)) } @@ -217,7 +213,7 @@ private[chisel3] object Converter { case d => d.specifiedDirection } - def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { // scalastyle:ignore cyclomatic.complexity line.size.limit + def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { case _: Clock => fir.ClockType case _: AsyncReset => fir.AsyncResetType case _: ResetType => fir.ResetType diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index d98bebcd..89bc4a63 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -14,7 +14,6 @@ import _root_.firrtl.PrimOps import scala.collection.immutable.NumericRange import scala.math.BigDecimal.RoundingMode -// scalastyle:off number.of.types case class PrimOp(name: String) { override def toString: String = name @@ -95,7 +94,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { protected def minWidth: Int if (forcedWidth) { require(widthArg.get >= minWidth, - s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") // scalastyle:ignore line.size.limit + s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") } } @@ -359,7 +358,6 @@ object IntervalRange { } } - //scalastyle:off method.name def Unknown: IntervalRange = range"[?,?].?" } @@ -390,7 +388,6 @@ sealed class IntervalRange( case _ => } - //scalastyle:off cyclomatic.complexity override def toString: String = { val binaryPoint = firrtlBinaryPoint match { case firrtlir.IntWidth(n) => s"$n" @@ -718,7 +715,6 @@ abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } -// scalastyle:off line.size.limit case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala index cf0afb10..8597b5c7 100644 --- a/core/src/main/scala/chisel3/package.scala +++ b/core/src/main/scala/chisel3/package.scala @@ -4,7 +4,7 @@ import chisel3.internal.firrtl.BinaryPoint /** This package contains the main chisel3 API. */ -package object chisel3 { // scalastyle:ignore package.object.name +package object chisel3 { import internal.firrtl.{Port, Width} import internal.Builder @@ -30,23 +30,23 @@ package object chisel3 { // scalastyle:ignore package.object.name implicit class fromBigIntToLiteral(bigint: BigInt) { /** Int to Bool conversion, allowing compact syntax like 1.B and 0.B */ - def B: Bool = bigint match { // scalastyle:ignore method.name + def B: Bool = bigint match { case bigint if bigint == 0 => Bool.Lit(false) case bigint if bigint == 1 => Bool.Lit(true) case bigint => Builder.error(s"Cannot convert $bigint to Bool, must be 0 or 1"); Bool.Lit(false) } /** Int to UInt conversion, recommended style for constants. */ - def U: UInt = UInt.Lit(bigint, Width()) // scalastyle:ignore method.name + def U: UInt = UInt.Lit(bigint, Width()) /** Int to SInt conversion, recommended style for constants. */ - def S: SInt = SInt.Lit(bigint, Width()) // scalastyle:ignore method.name + def S: SInt = SInt.Lit(bigint, Width()) /** Int to UInt conversion with specified width, recommended style for constants. */ - def U(width: Width): UInt = UInt.Lit(bigint, width) // scalastyle:ignore method.name + def U(width: Width): UInt = UInt.Lit(bigint, width) /** Int to SInt conversion with specified width, recommended style for constants. */ - def S(width: Width): SInt = SInt.Lit(bigint, width) // scalastyle:ignore method.name + def S(width: Width): SInt = SInt.Lit(bigint, width) /** Int to UInt conversion, recommended style for variables. */ @@ -68,10 +68,10 @@ package object chisel3 { // scalastyle:ignore package.object.name implicit class fromStringToLiteral(str: String) { /** String to UInt parse, recommended style for constants. */ - def U: UInt = str.asUInt() // scalastyle:ignore method.name + def U: UInt = str.asUInt() /** String to UInt parse with specified width, recommended style for constants. */ - def U(width: Width): UInt = str.asUInt(width) // scalastyle:ignore method.name + def U(width: Width): UInt = str.asUInt(width) /** String to UInt parse, recommended style for variables. */ @@ -97,13 +97,13 @@ package object chisel3 { // scalastyle:ignore package.object.name } implicit class fromIntToBinaryPoint(int: Int) { - def BP: BinaryPoint = BinaryPoint(int) // scalastyle:ignore method.name + def BP: BinaryPoint = BinaryPoint(int) } implicit class fromBooleanToLiteral(boolean: Boolean) { /** Boolean to Bool conversion, recommended style for constants. */ - def B: Bool = Bool.Lit(boolean) // scalastyle:ignore method.name + def B: Bool = Bool.Lit(boolean) /** Boolean to Bool conversion, recommended style for variables. */ @@ -136,7 +136,7 @@ package object chisel3 { // scalastyle:ignore package.object.name extends experimental.Interval.Implicits.fromBigDecimalToLiteralInterval(bigDecimal) implicit class fromIntToWidth(int: Int) { - def W: Width = Width(int) // scalastyle:ignore method.name + def W: Width = Width(int) } val WireInit = WireDefault |