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-rw-r--r--core/src/main/scala/chisel3/BlackBox.scala12
1 files changed, 8 insertions, 4 deletions
diff --git a/core/src/main/scala/chisel3/BlackBox.scala b/core/src/main/scala/chisel3/BlackBox.scala
index f618901f..c3cb3e66 100644
--- a/core/src/main/scala/chisel3/BlackBox.scala
+++ b/core/src/main/scala/chisel3/BlackBox.scala
@@ -92,8 +92,10 @@ package experimental {
private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
implicit val sourceInfo = UnlocatableSourceInfo
- for (x <- getModulePorts) {
- pushCommand(DefInvalid(sourceInfo, x.ref))
+ if (!parentCompileOptions.explicitInvalidate) {
+ for (x <- getModulePorts) {
+ pushCommand(DefInvalid(sourceInfo, x.ref))
+ }
}
}
}
@@ -192,8 +194,10 @@ abstract class BlackBox(
}
private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
- for ((_, port) <- _io.map(_.elements).getOrElse(Nil)) {
- pushCommand(DefInvalid(UnlocatableSourceInfo, port.ref))
+ if (!parentCompileOptions.explicitInvalidate) {
+ for ((_, port) <- _io.map(_.elements).getOrElse(Nil)) {
+ pushCommand(DefInvalid(UnlocatableSourceInfo, port.ref))
+ }
}
}
}