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-rw-r--r--core/src/main/scala/chisel3/internal/Binding.scala2
-rw-r--r--core/src/main/scala/chisel3/internal/Builder.scala2
-rw-r--r--core/src/main/scala/chisel3/internal/Namer.scala2
-rw-r--r--core/src/main/scala/chisel3/internal/firrtl/Converter.scala2
-rw-r--r--core/src/main/scala/chisel3/internal/firrtl/IR.scala17
5 files changed, 4 insertions, 21 deletions
diff --git a/core/src/main/scala/chisel3/internal/Binding.scala b/core/src/main/scala/chisel3/internal/Binding.scala
index 63936212..3a12afde 100644
--- a/core/src/main/scala/chisel3/internal/Binding.scala
+++ b/core/src/main/scala/chisel3/internal/Binding.scala
@@ -13,7 +13,7 @@ import scala.collection.immutable.VectorMap
object requireIsHardware {
def apply(node: Data, msg: String = ""): Unit = {
node._parent match { // Compatibility layer hack
- case Some(x: BaseModule) => x._compatAutoWrapPorts
+ case Some(x: BaseModule) => x._compatAutoWrapPorts()
case _ =>
}
if (!node.isSynthesizable) {
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 57f878aa..0a63bc74 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -791,7 +791,7 @@ object DynamicNamingStack {
prefixRef
}
- def length(): Int = Builder.namingStackOption.get.length
+ def length(): Int = Builder.namingStackOption.get.length()
}
/** Casts BigInt to Int, issuing an error when the input isn't representable. */
diff --git a/core/src/main/scala/chisel3/internal/Namer.scala b/core/src/main/scala/chisel3/internal/Namer.scala
index 23b5b7ba..45efa052 100644
--- a/core/src/main/scala/chisel3/internal/Namer.scala
+++ b/core/src/main/scala/chisel3/internal/Namer.scala
@@ -3,7 +3,6 @@
// This file contains part of the implementation of the naming static annotation system.
package chisel3.internal.naming
-import chisel3.experimental.NoChiselNamePrefix
import scala.collection.mutable.Stack
import scala.collection.mutable.ListBuffer
@@ -97,7 +96,6 @@ class NamingContext extends NamingContextInterface {
def name[T](obj: T, name: String): T = {
assert(!closed, "Can't name elements after namePrefix called")
obj match {
- case _: NoChiselNamePrefix => // Don't name things with NoChiselNamePrefix
case ref: AnyRef => items += ((ref, name))
case _ =>
}
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index c9719498..93676fef 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -160,8 +160,6 @@ private[chisel3] object Converter {
Some(fir.IsInvalid(convert(info), convert(arg, ctx, info)))
case e @ DefInstance(info, id, _) =>
Some(fir.DefInstance(convert(info), e.name, id.name))
- case e @ Stop(_, info, clock, ret) =>
- Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one, e.name))
case e @ Printf(_, info, clock, pable) =>
val (fmt, args) = unpack(pable, ctx)
Some(
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 8ed5ed07..0e0ebef2 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -332,12 +332,7 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
-// Note this is just deprecated which will cause deprecation warnings, use @nowarn
-@deprecated(
- "This API should never have been public, for Module port reflection, use DataMirror.modulePorts",
- "Chisel 3.5"
-)
+
case class Port(id: Data, dir: SpecifiedDirection)
case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
object Formal extends Enumeration {
@@ -345,15 +340,7 @@ object Formal extends Enumeration {
val Assume = Value("assume")
val Cover = Value("cover")
}
-case class Verification[T <: VerificationStatement](
- id: T,
- op: Formal.Value,
- sourceInfo: SourceInfo,
- clock: Arg,
- predicate: Arg,
- message: String)
- extends Definition
-@nowarn("msg=class Port") // delete when Port becomes private
+
abstract class Component extends Arg {
def id: BaseModule
def name: String