diff options
Diffstat (limited to 'core/src/main/scala/chisel3/internal')
5 files changed, 11 insertions, 32 deletions
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala index 46a2c134..c45a97f9 100644 --- a/core/src/main/scala/chisel3/internal/BiConnect.scala +++ b/core/src/main/scala/chisel3/internal/BiConnect.scala @@ -367,9 +367,6 @@ private[chisel3] object BiConnect { // This function checks if analog element-level attaching is allowed, then marks the Analog as connected def markAnalogConnected(analog: Analog, contextModule: BaseModule): Unit = { - analog.biConnectLocs.get(contextModule) match { - case Some(sl) => throw AttachAlreadyBulkConnectedException - case None => // Do nothing - } + println("not doing anything for analog till we have sourceinfos again") } } diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala index 0a63bc74..d62f2934 100644 --- a/core/src/main/scala/chisel3/internal/Builder.scala +++ b/core/src/main/scala/chisel3/internal/Builder.scala @@ -355,9 +355,9 @@ private[chisel3] trait HasId extends InstanceId { case Some(p) => p.circuitName } - private[chisel3] def getPublicFields(rootClass: Class[_]): Seq[java.lang.reflect.Method] = { + private[chisel3] def getPublicFields(rootClass: Class[?]): Seq[java.lang.reflect.Method] = { // Suggest names to nodes using runtime reflection - def getValNames(c: Class[_]): Set[String] = { + def getValNames(c: Class[?]): Set[String] = { if (c == rootClass) { Set() } else { @@ -726,7 +726,7 @@ private[chisel3] object Builder extends LazyLogging { } def getScalaMajorVersion: Int = { - val "2" :: major :: _ :: Nil = chisel3.BuildInfo.scalaVersion.split("\\.").toList + val "2" :: major :: _ :: Nil = chisel3.BuildInfo.scalaVersion.split("\\.").toList: @unchecked major.toInt } diff --git a/core/src/main/scala/chisel3/internal/Namer.scala b/core/src/main/scala/chisel3/internal/Namer.scala index 45efa052..0deb0c55 100644 --- a/core/src/main/scala/chisel3/internal/Namer.scala +++ b/core/src/main/scala/chisel3/internal/Namer.scala @@ -53,7 +53,7 @@ sealed trait NamingContextInterface { * so that actual naming calls (HasId.suggestName) can happen. * Recursively names descendants, for those whose return value have an associated name. */ - def namePrefix(prefix: String): String + def namePrefix(prefix: String): Unit } /** Dummy implementation to allow for naming annotations in a non-Builder context. diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index 3c4a01b2..08c96f48 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -96,7 +96,7 @@ private[chisel3] object Converter { val consts = e.args.collect { case ILit(i) => i } val args = e.args.flatMap { case _: ILit => None - case other => Some(convert(other, ctx, fir.NoInfo)) + case other => Some(convert(other, ctx)) } val expr = e.op.name match { case "mux" => @@ -168,24 +168,6 @@ private[chisel3] object Converter { e.name ) ) - case e @ Verification(_, op, clk, pred, msg) => - val firOp = op match { - case Formal.Assert => fir.Formal.Assert - case Formal.Assume => fir.Formal.Assume - case Formal.Cover => fir.Formal.Cover - } - None - // Some( - // fir.Verification( - // firOp, - // fir.NoInfo, - // convert(clk, ctx), - // convert(pred, ctx), - // firrtl.Utils.one, - // fir.StringLit(msg), - // e.name - // ) - // ) case _ => None } @@ -245,7 +227,7 @@ private[chisel3] object Converter { else frame.when.copy(conseq = fir.Block(stmts.result())) // Check if this when has an else cmdsIt.headOption match { - case Some(AltBegin(_)) => + case Some(AltBegin()) => assert(!frame.alt, "Internal Error! Unexpected when structure!") // Only 1 else per when scope = frame.copy(when = when, alt = true) :: scope.tail cmdsIt.next() // Consume the AltBegin diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index 6f993847..551b6138 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -365,10 +365,10 @@ case class Circuit( ) def copy( - name: String = name, - components: Seq[Component] = components, - annotations: Seq[ChiselAnnotation] = annotations, - renames: RenameMap = renames + name: String, + components: Seq[Component], + annotations: Seq[ChiselAnnotation], + renames: RenameMap ) = Circuit(name, components, annotations, renames, newAnnotations) } |