3 files changed, 7 insertions, 5 deletions
diff --git a/core/src/main/scala/chisel3/internal/Error.scala b/core/src/main/scala/chisel3/internal/Error.scala
index 730c9510..69042c3f 100644
--- a/core/src/main/scala/chisel3/internal/Error.scala
+++ b/core/src/main/scala/chisel3/internal/Error.scala
@@ -3,8 +3,10 @@
 package chisel3.internal
 
 import scala.annotation.tailrec
-import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
-import scala.util.control.NoStackTrace
+import scala.collection.mutable.{ArrayBuffer, LinkedHashMap, LinkedHashSet}
+import scala.util.Try
+import scala.util.control.{NoStackTrace, NonFatal}
+import scala.util.matching.Regex
 import _root_.logger.Logger
 
 object ExceptionHelpers {
@@ -191,7 +193,7 @@ private[chisel3] class ErrorLog(warningsAsErrors: Boolean) {
   }
 
   private def warn(m: => String, loc: Option[StackTraceElement]): LogEntry =
-    if (warningsAsErrors) new Error(m, loc) else new Warning(m, loc)
+    if (warningsAsErrors) new Error(m, loc) else new Info(m, None)
 
   /** Log a warning message */
   def warning(m: => String): Unit = {
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 9fee727c..81a35ddc 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -342,7 +342,7 @@ case class Circuit(
   ) = Circuit(name, components, annotations, renames, newAnnotations)
 
 }
-case class DefClass(id: Class[_], name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+// case class DefClass(id: Class[?], name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 object Circuit
     extends scala.runtime.AbstractFunction4[String, Seq[Component], Seq[ChiselAnnotation], RenameMap, Circuit] {
   def unapply(c: Circuit): Option[(String, Seq[Component], Seq[ChiselAnnotation], RenameMap)] = {
diff --git a/core/src/main/scala/chisel3/internal/package.scala b/core/src/main/scala/chisel3/internal/package.scala
index 25d9129f..2e1448a5 100644
--- a/core/src/main/scala/chisel3/internal/package.scala
+++ b/core/src/main/scala/chisel3/internal/package.scala
@@ -69,7 +69,7 @@ package object internal {
   private[chisel3] def _padHandleBool[A <: Bits](
     x:     A,
     width: Int
-  )(using Quotes): A = x match {
+  )(using Quotes, quoted.Type[A]): A = x match {
     case b: Bool if !b.isLit && width > 1 && Type.of[A] == Type.of[UInt] =>
       val _pad = Wire(UInt(width.W))
       _pad := b