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-rw-r--r--core/src/main/scala/chisel3/RawModule.scala9
1 files changed, 7 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 74e9db6c..27f16ad4 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -7,7 +7,7 @@ import scala.util.Try
import scala.language.experimental.macros
import chisel3.experimental.{BaseModule, BaseSim}
import chisel3.internal._
-import chisel3.internal.BaseModule.ModuleClone
+import chisel3.internal.BaseModule.{ModuleClone, InstanceClone}
import chisel3.internal.Builder._
import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo.UnlocatableSourceInfo
@@ -77,7 +77,8 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
// All suggestions are in, force names to every node.
for (id <- getIds) {
id match {
- case id: ModuleClone => id.setRefAndPortsRef(_namespace) // special handling
+ case id: ModuleClone[_] => id.setRefAndPortsRef(_namespace) // special handling
+ case id: InstanceClone[_] => id.setAsInstanceRef()
case id: BaseModule => id.forceName(None, default=id.desiredName, _namespace)
case id: MemBase[_] => id.forceName(None, default="MEM", _namespace)
case id: BaseSim => id.forceName(None, default="SIM", _namespace)
@@ -158,6 +159,10 @@ trait RequireSyncReset extends Module {
package object internal {
+ import scala.annotation.implicitNotFound
+ @implicitNotFound("You are trying to access a macro-only API. Please use the @public annotation instead.")
+ trait MacroGenerated
+
/** Marker trait for modules that are not true modules */
private[chisel3] trait PseudoModule extends BaseModule