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Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 5b609384..a1006594 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -80,15 +80,15 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) case id: Data => if (id.isSynthesizable) { id.topBinding match { - case OpBinding(_) => + case OpBinding(_, _) => id.forceName(Some(""), default="T", _namespace) - case MemoryPortBinding(_) => + case MemoryPortBinding(_, _) => id.forceName(None, default="MPORT", _namespace) case PortBinding(_) => id.forceName(None, default="PORT", _namespace) - case RegBinding(_) => + case RegBinding(_, _) => id.forceName(None, default="REG", _namespace) - case WireBinding(_) => + case WireBinding(_, _) => id.forceName(Some(""), default="WIRE", _namespace) case _ => // don't name literals } |