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-rw-r--r--core/src/main/scala/chisel3/RawModule.scala107
1 files changed, 61 insertions, 46 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index e977d918..b81372d8 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -8,7 +8,7 @@ import scala.language.experimental.macros
import scala.annotation.nowarn
import chisel3.experimental.BaseModule
import chisel3.internal._
-import chisel3.internal.BaseModule.{ModuleClone, InstanceClone}
+import chisel3.internal.BaseModule.{InstanceClone, ModuleClone}
import chisel3.internal.Builder._
import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo.UnlocatableSourceInfo
@@ -19,8 +19,7 @@ import _root_.firrtl.annotations.{IsModule, ModuleTarget}
* multiple IO() declarations.
*/
@nowarn("msg=class Port") // delete when Port becomes private
-abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
- extends BaseModule {
+abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends BaseModule {
//
// RTL construction internals
//
@@ -49,19 +48,22 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
port._computeName(None, None).orElse(names.get(port)) match {
case Some(name) =>
if (_namespace.contains(name)) {
- Builder.error(s"""Unable to name port $port to "$name" in $this,""" +
- " name is already taken by another port!")
+ Builder.error(
+ s"""Unable to name port $port to "$name" in $this,""" +
+ " name is already taken by another port!"
+ )
}
port.setRef(ModuleIO(this, _namespace.name(name)))
case None =>
- Builder.error(s"Unable to name port $port in $this, " +
- "try making it a public field of the Module")
+ Builder.error(
+ s"Unable to name port $port in $this, " +
+ "try making it a public field of the Module"
+ )
port.setRef(ModuleIO(this, "<UNNAMED>"))
}
}
}
-
private[chisel3] override def generateComponent(): Option[Component] = {
require(!_closed, "Can't generate module more than once")
_closed = true
@@ -79,29 +81,29 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
// All suggestions are in, force names to every node.
for (id <- getIds) {
id match {
- case id: ModuleClone[_] => id.setRefAndPortsRef(_namespace) // special handling
+ case id: ModuleClone[_] => id.setRefAndPortsRef(_namespace) // special handling
case id: InstanceClone[_] => id.setAsInstanceRef()
- case id: BaseModule => id.forceName(None, default=id.desiredName, _namespace)
- case id: MemBase[_] => id.forceName(None, default="MEM", _namespace)
- case id: stop.Stop => id.forceName(None, default="stop", _namespace)
- case id: assert.Assert => id.forceName(None, default="assert", _namespace)
- case id: assume.Assume => id.forceName(None, default="assume", _namespace)
- case id: cover.Cover => id.forceName(None, default="cover", _namespace)
- case id: printf.Printf => id.forceName(None, default="printf", _namespace)
- case id: Data =>
+ case id: BaseModule => id.forceName(None, default = id.desiredName, _namespace)
+ case id: MemBase[_] => id.forceName(None, default = "MEM", _namespace)
+ case id: stop.Stop => id.forceName(None, default = "stop", _namespace)
+ case id: assert.Assert => id.forceName(None, default = "assert", _namespace)
+ case id: assume.Assume => id.forceName(None, default = "assume", _namespace)
+ case id: cover.Cover => id.forceName(None, default = "cover", _namespace)
+ case id: printf.Printf => id.forceName(None, default = "printf", _namespace)
+ case id: Data =>
if (id.isSynthesizable) {
id.topBinding match {
case OpBinding(_, _) =>
- id.forceName(Some(""), default="T", _namespace)
+ id.forceName(Some(""), default = "T", _namespace)
case MemoryPortBinding(_, _) =>
- id.forceName(None, default="MPORT", _namespace)
+ id.forceName(None, default = "MPORT", _namespace)
case PortBinding(_) =>
- id.forceName(None, default="PORT", _namespace)
+ id.forceName(None, default = "PORT", _namespace)
case RegBinding(_, _) =>
- id.forceName(None, default="REG", _namespace)
+ id.forceName(None, default = "REG", _namespace)
case WireBinding(_, _) =>
- id.forceName(Some(""), default="WIRE", _namespace)
- case _ => // don't name literals
+ id.forceName(Some(""), default = "WIRE", _namespace)
+ case _ => // don't name literals
}
} // else, don't name unbound types
}
@@ -110,19 +112,20 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
closeUnboundIds(names)
- val firrtlPorts = getModulePorts map { port: Data =>
+ val firrtlPorts = getModulePorts.map { port: Data =>
// Special case Vec to make FIRRTL emit the direction of its
// element.
// Just taking the Vec's specifiedDirection is a bug in cases like
// Vec(Flipped()), since the Vec's specifiedDirection is
// Unspecified.
val direction = port match {
- case v: Vec[_] => v.specifiedDirection match {
- case SpecifiedDirection.Input => SpecifiedDirection.Input
- case SpecifiedDirection.Output => SpecifiedDirection.Output
- case SpecifiedDirection.Flip => SpecifiedDirection.flip(v.sample_element.specifiedDirection)
- case SpecifiedDirection.Unspecified => v.sample_element.specifiedDirection
- }
+ case v: Vec[_] =>
+ v.specifiedDirection match {
+ case SpecifiedDirection.Input => SpecifiedDirection.Input
+ case SpecifiedDirection.Output => SpecifiedDirection.Output
+ case SpecifiedDirection.Flip => SpecifiedDirection.flip(v.sample_element.specifiedDirection)
+ case SpecifiedDirection.Unspecified => v.sample_element.specifiedDirection
+ }
case _ => port.specifiedDirection
}
@@ -134,7 +137,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
// unless the client wants explicit control over their generation.
val invalidateCommands = {
if (!compileOptions.explicitInvalidate) {
- getModulePorts map { port => DefInvalid(UnlocatableSourceInfo, port.ref) }
+ getModulePorts.map { port => DefInvalid(UnlocatableSourceInfo, port.ref) }
} else {
Seq()
}
@@ -204,13 +207,15 @@ package object internal {
.map(_.forceFinalName("io"))
.orElse {
// Fallback if reflection fails, user can wrap in IO(...)
- self.findPort("io")
- .collect { case r: Record => r }
- }.getOrElse(throwException(
- s"Compatibility mode Module '$this' must have a 'val io' Bundle. " +
- "If there is such a field and you still see this error, autowrapping has failed (sorry!). " +
- "Please wrap the Bundle declaration in IO(...)."
- ))
+ self.findPort("io").collect { case r: Record => r }
+ }
+ .getOrElse(
+ throwException(
+ s"Compatibility mode Module '$this' must have a 'val io' Bundle. " +
+ "If there is such a field and you still see this error, autowrapping has failed (sorry!). " +
+ "Please wrap the Bundle declaration in IO(...)."
+ )
+ )
}
/** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor
@@ -221,15 +226,19 @@ package object internal {
*/
abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) extends Module {
// Provide a non-deprecated constructor
- def this(override_clock: Option[Clock] = None, override_reset: Option[Bool]=None)
- (implicit moduleCompileOptions: CompileOptions) = {
+ def this(
+ override_clock: Option[Clock] = None,
+ override_reset: Option[Bool] = None
+ )(
+ implicit moduleCompileOptions: CompileOptions
+ ) = {
this()
this.override_clock = override_clock
this.override_reset = override_reset
}
def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) =
this(Option(_clock), None)(moduleCompileOptions)
- def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) =
+ def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) =
this(None, Option(_reset))(moduleCompileOptions)
def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) =
this(Option(_clock), Option(_reset))(moduleCompileOptions)
@@ -240,12 +249,15 @@ package object internal {
protected def _compatIoPortBound() = portsContains(_io)
private[chisel3] override def generateComponent(): Option[Component] = {
- _compatAutoWrapPorts() // pre-IO(...) compatibility hack
+ _compatAutoWrapPorts() // pre-IO(...) compatibility hack
// Restrict IO to just io, clock, and reset
require(_io != null, "Module must have io")
require(portsContains(_io), "Module must have io wrapped in IO(...)")
- require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO")
+ require(
+ (portsContains(clock)) && (portsContains(reset)),
+ "Internal error, module did not have clock or reset as IO"
+ )
require(portsSize == 3, "Module must only have io, clock, and reset as IO")
super.generateComponent()
@@ -265,8 +277,10 @@ package object internal {
* '''Do not use this class in user code'''. Use whichever `BlackBox` is imported by your wildcard
* import (preferably `import chisel3._`).
*/
- abstract class LegacyBlackBox(params: Map[String, Param] = Map.empty[String, Param])
- (implicit moduleCompileOptions: CompileOptions)
+ abstract class LegacyBlackBox(
+ params: Map[String, Param] = Map.empty[String, Param]
+ )(
+ implicit moduleCompileOptions: CompileOptions)
extends chisel3.BlackBox(params) {
override private[chisel3] lazy val _io: Record = reflectivelyFindValIO(this)
@@ -305,5 +319,6 @@ package object internal {
*
* @note this is a val instead of an object because of the need to wrap in Module(...)
*/
- private[chisel3] val ViewParent = Module.do_apply(new ViewParentAPI)(UnlocatableSourceInfo, ExplicitCompileOptions.Strict)
+ private[chisel3] val ViewParent =
+ Module.do_apply(new ViewParentAPI)(UnlocatableSourceInfo, ExplicitCompileOptions.Strict)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 19:40:23 +0000