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-rw-r--r--core/src/main/scala/chisel3/Module.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index ba2d2e32..9315a44b 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -709,9 +709,9 @@ package experimental {
data match {
case record: Record =>
val compatRecord = !record.compileOptions.dontAssumeDirectionality
- record.getElements.foreach(assignCompatDir(_, compatRecord))
+ record.elementsIterator.foreach(assignCompatDir(_, compatRecord))
case vec: Vec[_] =>
- vec.getElements.foreach(assignCompatDir(_, insideCompat))
+ vec.elementsIterator.foreach(assignCompatDir(_, insideCompat))
}
case SpecifiedDirection.Input | SpecifiedDirection.Output => // forced assign, nothing to do
}