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-rw-r--r--core/src/main/scala/chisel3/Module.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index d03122f9..ba2d2e32 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -275,7 +275,7 @@ package internal {
private[chisel3] def setRefAndPortsRef(namespace: Namespace): Unit = {
val record = _portsRecord
// Use .forceName to re-use default name resolving behavior
- record.forceName(None, default = this.desiredName, namespace)
+ record.forceName(default = this.desiredName, namespace)
// Now take the Ref that forceName set and convert it to the correct Arg
val instName = record.getRef match {
case Ref(name) => name
@@ -497,7 +497,7 @@ package experimental {
private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = {
for (port <- getModulePorts) {
- port._computeName(None, None).orElse(names.get(port)) match {
+ port._computeName(None).orElse(names.get(port)) match {
case Some(name) =>
if (_namespace.contains(name)) {
Builder.error(