1 files changed, 25 insertions, 10 deletions

diff --git a/core/src/main/scala/chisel3/CompileOptions.scala b/core/src/main/scala/chisel3/CompileOptions.scala
index 2764b652..d7d30306 100644
--- a/core/src/main/scala/chisel3/CompileOptions.scala
+++ b/core/src/main/scala/chisel3/CompileOptions.scala
@@ -6,25 +6,37 @@ import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
 
 trait CompileOptions {
-  // Should Record connections require a strict match of fields.
-  // If true and the same fields aren't present in both source and sink, a MissingFieldException,
-  // MissingLeftFieldException, or MissingRightFieldException will be thrown.
+
+  /** Should Record connections require a strict match of fields.
+    *
+    * If true and the same fields aren't present in both source and sink, a MissingFieldException,
+    * MissingLeftFieldException, or MissingRightFieldException will be thrown.
+    */
   val connectFieldsMustMatch: Boolean
-  // When creating an object that takes a type argument, the argument must be unbound (a pure type).
+
+  /** When creating an object that takes a type argument, the argument must be unbound (a pure type). */
   val declaredTypeMustBeUnbound: Boolean
-  // If a connection operator fails, don't try the connection with the operands (source and sink) reversed.
+
+  /** If a connection operator fails, don't try the connection with the operands (source and sink) reversed. */
   val dontTryConnectionsSwapped: Boolean
-  // If connection directionality is not explicit, do not use heuristics to attempt to determine it.
+
+  /** If connection directionality is not explicit, do not use heuristics to attempt to determine it. */
   val dontAssumeDirectionality: Boolean
-  // Check that referenced Data have actually been declared.
+
+  /** Check that referenced Data have actually been declared. */
   val checkSynthesizable: Boolean
-  // Require explicit assignment of DontCare to generate "x is invalid"
+
+  /** Require explicit assignment of DontCare to generate "x is invalid" */
   val explicitInvalidate: Boolean
-  // Should the reset type of Module be a Bool or a Reset
+
+  /** Should the reset type of Module be a Bool or a Reset */
   val inferModuleReset: Boolean
 
   /** If marked true, then any Module which consumes `inferModuleReset=false` must also mix in [[RequireSyncReset]] */
   def migrateInferModuleReset: Boolean = false
+
+  /** Should connects emit as firrtl <= instead of <- */
+  def emitStrictConnects: Boolean = true
 }
 
 object CompileOptions {
@@ -39,6 +51,7 @@ object CompileOptions {
 }
 
 object ExplicitCompileOptions {
+
   case class CompileOptionsClass(
     // Should Record connections require a strict match of fields.
     // If true and the same fields aren't present in both source and sink, a MissingFieldException,
@@ -68,7 +81,9 @@ object ExplicitCompileOptions {
     checkSynthesizable = false,
     explicitInvalidate = false,
     inferModuleReset = false
-  )
+  ) {
+    override def emitStrictConnects = false
+  }
 
   // Collection of "strict" connection compile options, preferred for new code.
   implicit val Strict = new CompileOptionsClass(