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Diffstat (limited to 'core/src/main/scala/chisel3/Clock.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Clock.scala | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/core/src/main/scala/chisel3/Clock.scala b/core/src/main/scala/chisel3/Clock.scala index 64e91c42..aee6bc5a 100644 --- a/core/src/main/scala/chisel3/Clock.scala +++ b/core/src/main/scala/chisel3/Clock.scala @@ -2,7 +2,6 @@ package chisel3 -import scala.language.experimental.macros import chisel3.internal.Builder.pushOp import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo._ @@ -33,17 +32,13 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element def toPrintable: Printable = PString("CLOCK") /** Returns the contents of the clock wire as a [[Bool]]. */ - final def asBool: Bool = macro SourceInfoTransform.noArg - @deprecated( "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5" ) - final def asBool(dummy: Int*): Bool = macro SourceInfoTransform.noArgDummy - - def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt.asBool + def asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt.asBool - override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp( + override def asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp( DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref) ) private[chisel3] override def connectFromBits( |