1 files changed, 12 insertions, 9 deletions
diff --git a/core/src/main/scala/chisel3/BlackBox.scala b/core/src/main/scala/chisel3/BlackBox.scala
index 89c4ccd3..2f04fb2e 100644
--- a/core/src/main/scala/chisel3/BlackBox.scala
+++ b/core/src/main/scala/chisel3/BlackBox.scala
@@ -145,27 +145,30 @@ abstract class BlackBox(
     extends BaseBlackBox {
 
   // Find a Record port named "io" for purposes of stripping the prefix
-  private[chisel3] lazy val _io: Record =
+  private[chisel3] lazy val _io: Option[Record] =
     this
       .findPort("io")
       .collect { case r: Record => r } // Must be a Record
-      .getOrElse(null) // null handling occurs in generateComponent
 
   // Allow access to bindings from the compatibility package
-  protected def _compatIoPortBound() = portsContains(_io)
+  protected def _compatIoPortBound() = _io.exists(portsContains(_))
 
   private[chisel3] override def generateComponent(): Option[Component] = {
     _compatAutoWrapPorts() // pre-IO(...) compatibility hack
 
     // Restrict IO to just io, clock, and reset
-    require(_io != null, "BlackBox must have a port named 'io' of type Record!")
-    require(portsContains(_io), "BlackBox must have io wrapped in IO(...)")
+    if (!_io.forall(portsContains)) {
+      throwException(s"BlackBox '$this' must have a port named 'io' of type Record wrapped in IO(...)!")
+    }
+
     require(portsSize == 1, "BlackBox must only have one IO, called `io`")
 
     require(!_closed, "Can't generate module more than once")
     _closed = true
 
-    val namedPorts = _io.elements.toSeq.reverse // ListMaps are stored in reverse order
+    val io = _io.get
+
+    val namedPorts = io.elements.toSeq.reverse // ListMaps are stored in reverse order
 
     // There is a risk of user improperly attempting to connect directly with io
     // Long term solution will be to define BlackBox IO differently as part of
@@ -181,18 +184,18 @@ abstract class BlackBox(
     // of the io bundle, but NOT on the io bundle itself.
     // Doing so would cause the wrong names to be assigned, since their parent
     // is now the module itself instead of the io bundle.
-    for (id <- getIds; if id ne _io) {
+    for (id <- getIds; if id ne io) {
       id._onModuleClose
     }
 
     val firrtlPorts = namedPorts.map { namedPort => Port(namedPort._2, namedPort._2.specifiedDirection) }
-    val component = DefBlackBox(this, name, firrtlPorts, _io.specifiedDirection, params)
+    val component = DefBlackBox(this, name, firrtlPorts, io.specifiedDirection, params)
     _component = Some(component)
     _component
   }
 
   private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
-    for ((_, port) <- _io.elements) {
+    for ((_, port) <- _io.map(_.elements).getOrElse(Nil)) {
       pushCommand(DefInvalid(UnlocatableSourceInfo, port.ref))
     }
   }