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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala15
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala32
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala21
3 files changed, 43 insertions, 25 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 26c971b3..559a55bc 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -21,6 +21,21 @@ sealed abstract class Aggregate extends Data {
pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten)
+ def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
+ var i = 0
+ val wire = Wire(this.chiselCloneType)
+ val bits =
+ if (that.width.known && that.width.get >= wire.width.get) {
+ that
+ } else {
+ Wire(that.cloneTypeWidth(wire.width), init = that)
+ }
+ for (x <- wire.flatten) {
+ x := x.fromBits(bits(i + x.getWidth-1, i))
+ i += x.getWidth
+ }
+ wire.asInstanceOf[this.type]
+ }
}
object Vec {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index c5fc10e7..e885f1ee 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -292,12 +292,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
pushOp(DefPrim(sourceInfo, UInt(w), ConcatOp, this.ref, that.ref))
}
- override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
- val res = Wire(this, null).asInstanceOf[this.type]
- res := that
- res
- }
-
/** Default print as [[Decimal]] */
final def toPrintable: Printable = Decimal(this)
}
@@ -519,6 +513,14 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
throwException(s"cannot call $this.asFixedPoint(binaryPoint=$binaryPoint), you must specify a known binaryPoint")
}
}
+ def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
+ val res = Wire(this, null).asInstanceOf[this.type]
+ res := (that match {
+ case u: UInt => u
+ case _ => that.asUInt
+ })
+ res
+ }
}
// This is currently a factory because both Bits and UInt inherit it.
@@ -655,6 +657,14 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
throwException(s"cannot call $this.asFixedPoint(binaryPoint=$binaryPoint), you must specify a known binaryPoint")
}
}
+ def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
+ val res = Wire(this, null).asInstanceOf[this.type]
+ res := (that match {
+ case s: SInt => s
+ case _ => that.asSInt
+ })
+ res
+ }
}
trait SIntFactory {
@@ -916,13 +926,15 @@ sealed class FixedPoint private (width: Width, val binaryPoint: BinaryPoint, lit
override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref))
override def do_asSInt(implicit sourceInfo: SourceInfo): SInt = pushOp(DefPrim(sourceInfo, SInt(this.width), AsSIntOp, ref))
- //TODO(chick): Consider "convert" as an arithmetic conversion to UInt/SInt
-
- override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
+ def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
val res = Wire(this, null).asInstanceOf[this.type]
- res := that.asFixedPoint(this.binaryPoint)
+ res := (that match {
+ case fp: FixedPoint => fp.asSInt.asFixedPoint(this.binaryPoint)
+ case _ => that.asFixedPoint(this.binaryPoint)
+ })
res
}
+ //TODO(chick): Consider "convert" as an arithmetic conversion to UInt/SInt
}
/** Use PrivateObject to force users to specify width and binaryPoint by name
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 57ed0c59..6e80f045 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -238,21 +238,7 @@ abstract class Data extends HasId {
*/
def fromBits(that: Bits): this.type = macro CompileOptionsTransform.thatArg
- def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
- var i = 0
- val wire = Wire(this.chiselCloneType)
- val bits =
- if (that.width.known && that.width.get >= wire.width.get) {
- that
- } else {
- Wire(that.cloneTypeWidth(wire.width), init = that)
- }
- for (x <- wire.flatten) {
- x := bits(i + x.getWidth-1, i)
- i += x.getWidth
- }
- wire.asInstanceOf[this.type]
- }
+ def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type
/** Packs the value of this object as plain Bits.
*
@@ -337,4 +323,9 @@ sealed class Clock extends Element(Width(1)) {
def toPrintable: Printable = PString("CLOCK")
override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref))
+ override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = {
+ val ret = Wire(this.cloneType)
+ ret := that
+ ret.asInstanceOf[this.type]
+ }
}