diff options
Diffstat (limited to 'chiselFrontend')
13 files changed, 82 insertions, 101 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala new file mode 100644 index 00000000..2e5c64aa --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala @@ -0,0 +1,53 @@ +// See LICENSE for license details. + +package chisel3 + +import scala.language.experimental.macros + +trait CompileOptions { + // Should Bundle connections require a strict match of fields. + // If true and the same fields aren't present in both source and sink, a MissingFieldException, + // MissingLeftFieldException, or MissingRightFieldException will be thrown. + val connectFieldsMustMatch: Boolean + // When creating an object that takes a type argument, the argument must be unbound (a pure type). + val declaredTypeMustBeUnbound: Boolean + // Module IOs should be wrapped in an IO() to define their bindings before the reset of the module is defined. + val requireIOWrap: Boolean + // If a connection operator fails, don't try the connection with the operands (source and sink) reversed. + val dontTryConnectionsSwapped: Boolean + // If connection directionality is not explicit, do not use heuristics to attempt to determine it. + val dontAssumeDirectionality: Boolean +} + +trait ImplicitCompileOptions extends CompileOptions + +object ImplicitCompileOptions { + // Provides a low priority Strict default. Can be overridden by importing the NotStrict option. + implicit def materialize: ImplicitCompileOptions = chisel3.ExplicitCompileOptions.Strict +} + +// Define a more-specific trait which should be perferred if both are available. +trait ExplicitImplicitCompileOptions extends ImplicitCompileOptions + +object ExplicitCompileOptions { + // Collection of "not strict" connection compile options. + // These provide compatibility with existing code. + // import chisel3.ExplicitCompileOptions.NotStrict + implicit object NotStrict extends ExplicitImplicitCompileOptions { + val connectFieldsMustMatch = false + val declaredTypeMustBeUnbound = false + val requireIOWrap = false + val dontTryConnectionsSwapped = false + val dontAssumeDirectionality = false + } + + // Collection of "strict" connection compile options, preferred for new code. + // import chisel3.ExplicitCompileOptions.Strict + implicit object Strict extends ExplicitImplicitCompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = true + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/NotStrict.scala b/chiselFrontend/src/main/scala/chisel3/NotStrict.scala deleted file mode 100644 index bb390e7c..00000000 --- a/chiselFrontend/src/main/scala/chisel3/NotStrict.scala +++ /dev/null @@ -1,16 +0,0 @@ -// See LICENSE for license details. - -package chisel3 - -import chisel3.internal.ExplicitCompileOptions - - -object NotStrict { - implicit object CompileOptions extends ExplicitCompileOptions { - val connectFieldsMustMatch = false - val declaredTypeMustBeUnbound = false - val requireIOWrap = false - val dontTryConnectionsSwapped = false - val dontAssumeDirectionality = false - } -} diff --git a/chiselFrontend/src/main/scala/chisel3/Strict.scala b/chiselFrontend/src/main/scala/chisel3/Strict.scala deleted file mode 100644 index 70240429..00000000 --- a/chiselFrontend/src/main/scala/chisel3/Strict.scala +++ /dev/null @@ -1,16 +0,0 @@ -// See LICENSE for license details. - -package chisel3 - -import chisel3.internal.ExplicitCompileOptions - - -object Strict { - implicit object CompileOptions extends ExplicitCompileOptions { - val connectFieldsMustMatch = true - val declaredTypeMustBeUnbound = true - val requireIOWrap = true - val dontTryConnectionsSwapped = true - val dontAssumeDirectionality = true - } -} diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index a0eefbfe..b363c572 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -10,7 +10,7 @@ import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform} -import chisel3.NotStrict.CompileOptions +import chisel3.ImplicitCompileOptions /** An abstract class for data types that solely consist of (are an aggregate * of) other Data objects. @@ -152,27 +152,27 @@ sealed class Vec[T <: Data] private (gen: T, val length: Int) * * @note the length of this Vec must match the length of the input Seq */ - def <> (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ExplicitCompileOptions): Unit = { + def <> (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ImplicitCompileOptions): Unit = { require(this.length == that.length) for ((a, b) <- this zip that) a <> b } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ExplicitCompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] + def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ImplicitCompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] /** Strong bulk connect, assigning elements in this Vec from elements in a Seq. * * @note the length of this Vec must match the length of the input Seq */ - def := (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ExplicitCompileOptions): Unit = { + def := (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ImplicitCompileOptions): Unit = { require(this.length == that.length) for ((a, b) <- this zip that) a := b } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def := (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ExplicitCompileOptions): Unit = this connect that + def := (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: ImplicitCompileOptions): Unit = this connect that /** Creates a dynamically indexed read or write accessor into the array. */ @@ -199,7 +199,7 @@ sealed class Vec[T <: Data] private (gen: T, val length: Int) @deprecated("Use Vec.apply instead", "chisel3") def write(idx: UInt, data: T): Unit = { - apply(idx).:=(data)(DeprecatedSourceInfo, chisel3.NotStrict.CompileOptions) + apply(idx).:=(data)(DeprecatedSourceInfo, chisel3.ExplicitCompileOptions.NotStrict) } override def cloneType: this.type = { diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala index ce70a19a..a6b9cda3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -6,7 +6,7 @@ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.Connect import scala.language.experimental.macros import chisel3.internal.sourceinfo._ -import chisel3.internal.ExplicitCompileOptions +import chisel3.ImplicitCompileOptions /** * BiConnect.connect executes a bidirectional connection element-wise. @@ -50,7 +50,7 @@ object BiConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, left: Data, right: Data, context_mod: Module): Unit = + def connect(sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, left: Data, right: Data, context_mod: Module): Unit = (left, right) match { // Handle element case (root case) case (left_e: Element, right_e: Element) => { @@ -110,7 +110,7 @@ object BiConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, left: Element, right: Element, context_mod: Module): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, left: Element, right: Element, context_mod: Module): Unit = { import Direction.{Input, Output} // Using extensively so import these // If left or right have no location, assume in context module // This can occur if one of them is a literal, unbound will error previously diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 938eeb1f..12c99104 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -10,7 +10,7 @@ import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform, UIntTransform, MuxTransform} import chisel3.internal.firrtl.PrimOp._ -import chisel3.NotStrict.CompileOptions +//import chisel3.ImplicitCompileOptions.NotStrict /** Element is a leaf data type: it cannot contain other Data objects. Example * uses are for representing primitive data types, like integers and bits. diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 7b0cf3f7..7e61ec72 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -5,7 +5,7 @@ package chisel3.core import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{ModuleIO, DefInvalid} import chisel3.internal.sourceinfo.SourceInfo -import chisel3.NotStrict.CompileOptions +//import chisel3.ExplicitCompileOptions.NotStrict /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 52bc8128..1b08374a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -9,7 +9,7 @@ import chisel3.internal.Builder.{pushCommand, pushOp} import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform} import chisel3.internal.firrtl.PrimOp.AsUIntOp -import chisel3.NotStrict.CompileOptions +import chisel3.ImplicitCompileOptions sealed abstract class Direction(name: String) { override def toString: String = name @@ -126,7 +126,7 @@ abstract class Data extends HasId { private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = throwException(s"cannot connect ${this} and ${that}") - private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = { + private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = { Binding.checkSynthesizable(this, s"'this' ($this)") Binding.checkSynthesizable(that, s"'that' ($that)") try { @@ -138,7 +138,7 @@ abstract class Data extends HasId { ) } } - private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = { + private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = { Binding.checkSynthesizable(this, s"'this' ($this)") Binding.checkSynthesizable(that, s"'that' ($that)") try { @@ -167,8 +167,8 @@ abstract class Data extends HasId { } clone } - final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ExplicitCompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) - final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ExplicitCompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) + final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ImplicitCompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) + final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ImplicitCompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) def litArg(): Option[LitArg] = None def litValue(): BigInt = litArg.get.num def isLit(): Boolean = litArg.isDefined @@ -260,7 +260,7 @@ object Wire { do_apply(t, init)(UnlocatableSourceInfo) def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = { - val x = Reg.makeType(chisel3.NotStrict.CompileOptions, t, null.asInstanceOf[T], init) + val x = Reg.makeType(chisel3.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init) // Bind each element of x to being a Wire Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t") @@ -294,7 +294,7 @@ sealed class Clock extends Element(Width(1)) { private[core] def cloneTypeWidth(width: Width): this.type = cloneType private[chisel3] def toType = "Clock" - override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = that match { + override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = that match { case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions) case _ => super.badConnect(that)(sourceInfo) } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index 5eaaf262..d762ef5e 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -8,7 +8,7 @@ import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform} -import chisel3.NotStrict.CompileOptions +//import chisel3.ExplicitCompileOptions.NotStrict object Mem { @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3") diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 03e4f1b7..f4b36888 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -9,7 +9,7 @@ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ import chisel3.internal.firrtl.{Command => _, _} import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo} -import chisel3.NotStrict.CompileOptions +import chisel3.ImplicitCompileOptions object Module { /** A wrapper method that all Module instantiations must be wrapped in @@ -51,7 +51,7 @@ object Module { */ abstract class Module( override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) - (implicit moduleCompileOptions: ExplicitCompileOptions) + (implicit moduleCompileOptions: ImplicitCompileOptions) extends HasId { // _clock and _reset can be clock and reset in these 2ary constructors // once chisel2 compatibility issues are resolved diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala index 1925171b..38030d49 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala @@ -6,7 +6,7 @@ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.Connect import scala.language.experimental.macros import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo, WireTransform} -import chisel3.internal.ExplicitCompileOptions +import chisel3.ImplicitCompileOptions /** * MonoConnect.connect executes a mono-directional connection element-wise. @@ -56,7 +56,7 @@ object MonoConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, sink: Data, source: Data, context_mod: Module): Unit = + def connect(sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, sink: Data, source: Data, context_mod: Module): Unit = (sink, source) match { // Handle element case (root case) case (sink_e: Element, source_e: Element) => { @@ -103,7 +103,7 @@ object MonoConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, sink: Element, source: Element, context_mod: Module): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, sink: Element, source: Element, context_mod: Module): Unit = { import Direction.{Input, Output} // Using extensively so import these // If source has no location, assume in context module // This can occur if is a literal, unbound will error previously diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index 2569e9ea..1bdfb40f 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -6,9 +6,10 @@ import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} +import chisel3.ImplicitCompileOptions object Reg { - private[core] def makeType[T <: Data](compileOptions: ExplicitCompileOptions, t: T = null, next: T = null, init: T = null): T = { + private[core] def makeType[T <: Data](compileOptions: ImplicitCompileOptions, t: T = null, next: T = null, init: T = null): T = { if (t ne null) { if (compileOptions.declaredTypeMustBeUnbound) { Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?") @@ -40,7 +41,7 @@ object Reg { * is a valid value. In those cases, you can either use the outType only Reg * constructor or pass in `null.asInstanceOf[T]`. */ - def apply[T <: Data](t: T = null, next: T = null, init: T = null)(implicit sourceInfo: SourceInfo, compileOptions: ExplicitCompileOptions): T = + def apply[T <: Data](t: T = null, next: T = null, init: T = null)(implicit sourceInfo: SourceInfo, compileOptions: ImplicitCompileOptions): T = // Scala macros can't (yet) handle named or default arguments. do_apply(t, next, init)(sourceInfo, compileOptions) @@ -49,9 +50,9 @@ object Reg { * * @param outType: data type for the register */ - def apply[T <: Data](outType: T)(implicit sourceInfo: SourceInfo, compileOptions: ExplicitCompileOptions): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])(sourceInfo, compileOptions) + def apply[T <: Data](outType: T)(implicit sourceInfo: SourceInfo, compileOptions: ImplicitCompileOptions): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])(sourceInfo, compileOptions) - def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: ExplicitCompileOptions = chisel3.NotStrict.CompileOptions): T = { + def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: ImplicitCompileOptions = chisel3.ExplicitCompileOptions.NotStrict): T = { // TODO: write this in a way that doesn't need nulls (bad Scala style), // null.asInstanceOf[T], and two constructors. Using Option types are an // option, but introduces cumbersome syntax (wrap everything in a Some()). diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala deleted file mode 100644 index 2b913908..00000000 --- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala +++ /dev/null @@ -1,41 +0,0 @@ -// See LICENSE for license details. - -package chisel3.internal - -import scala.language.experimental.macros -import scala.reflect.macros.blackbox.Context - -trait CompileOptions { - // Should Bundle connections require a strict match of fields. - // If true and the same fields aren't present in both source and sink, a MissingFieldException, - // MissingLeftFieldException, or MissingRightFieldException will be thrown. - val connectFieldsMustMatch: Boolean - val declaredTypeMustBeUnbound: Boolean - val requireIOWrap: Boolean - val dontTryConnectionsSwapped: Boolean - val dontAssumeDirectionality: Boolean -} - -trait ExplicitCompileOptions extends CompileOptions - -object ExplicitCompileOptions { - // Provides a low priority Strict default. Can be overridden by importing the NotStrict option. - implicit def materialize: ExplicitCompileOptions = chisel3.Strict.CompileOptions -} - -///** Initialize compilation options from a string map. -// * -// * @param optionsMap the map from "option" to "value" -// */ -//class CompileOptions(optionsMap: Map[String, String]) { -// // The default for settings related to "strictness". -// val strictDefault: String = optionsMap.getOrElse("strict", "false") -// // Should Bundle connections require a strict match of fields. -// // If true and the same fields aren't present in both source and sink, a MissingFieldException, -// // MissingLeftFieldException, or MissingRightFieldException will be thrown. -// val connectFieldsMustMatch: Boolean = optionsMap.getOrElse("connectFieldsMustMatch", strictDefault).toBoolean -// val declaredTypeMustBeUnbound: Boolean = optionsMap.getOrElse("declaredTypeMustBeUnbound", strictDefault).toBoolean -// val requireIOWrap: Boolean = optionsMap.getOrElse("requireIOWrap", strictDefault).toBoolean -// val dontTryConnectionsSwapped: Boolean = optionsMap.getOrElse("dontTryConnectionsSwapped", strictDefault).toBoolean -// val dontAssumeDirectionality: Boolean = optionsMap.getOrElse("dontAssumeDirectionality", strictDefault).toBoolean -//} |