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-rw-r--r--chiselFrontend/src/main/scala/chisel3/Bits.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala
index 96eb74a4..43c34d9d 100644
--- a/chiselFrontend/src/main/scala/chisel3/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala
@@ -989,7 +989,7 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Elem
this.getClass == that.getClass
override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
- case _: Reset => super.connect(that)(sourceInfo, connectCompileOptions)
+ case _: Reset | DontCare => super.connect(that)(sourceInfo, connectCompileOptions)
case _ => super.badConnect(that)(sourceInfo)
}
@@ -1036,7 +1036,7 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends El
this.getClass == that.getClass
override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
- case _: AsyncReset => super.connect(that)(sourceInfo, connectCompileOptions)
+ case _: AsyncReset | DontCare => super.connect(that)(sourceInfo, connectCompileOptions)
case _ => super.badConnect(that)(sourceInfo)
}