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Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index 3fe78010..c5862974 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -156,6 +156,7 @@ sealed class SyncReadMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) { def do_read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { val a = Wire(UInt()) + a := DontCare var port: Option[T] = None when (enable) { a := addr |